Shared-Current Clock Driver Topology for Low-Power Large Arrays
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Solution Overview
Problem
Existing low power clocking solutions for large arrays consume excessive power due to the use of broadband drivers, leading to high uncorrelated jitter and inferior dynamic range per milliwatt metric, particularly in clock distribution routes.
Innovation Solution
A clock driver circuit comprising a multiple phase divider and a buffer that share the same current from a supply rail, with the buffer providing impedance transformation to prevent kickback noise and reduce power consumption, allowing for efficient low power clock distribution with reduced jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If broadband drivers are used to drive clock signals in large arrays, then the clock distribution reaches all array elements, but power consumption increases significantly
Solution Approach 1:
The clock distribution system is segmented into multiple narrowband clock drivers, each serving a specific frequency range and subset of array elements. This segmentation allows each driver to operate efficiently at its designated frequency rather than requiring a single broadband driver to cover all frequencies, thereby reducing overall power consumption while maintaining comprehensive clock distribution coverage.
2Manufacturing precision
If broadband drivers are used to provide square waveshape pulses, then duty cycle correction is achieved, but uncorrelated jitter increases
Solution Approach 1:
Each narrowband clock driver is optimized with specific circuit characteristics tailored to its operating frequency range. This local optimization allows each driver to provide accurate duty cycle correction for its specific frequency band while introducing minimal jitter, whereas a broadband driver would have to use generic circuitry that performs less optimally across all frequencies.
3Manufacturing precision
If H-tree layout with individual clock receivers is used, then clock levels are corrected, but uncorrelated out of band jitter increases
Solution Approach 1:
The clock level correction function is extracted from individual distributed clock receivers and consolidated into centralized buffer circuits within the narrowband clock drivers. This extraction eliminates the need for multiple separate receivers that would each introduce independent jitter, while still providing necessary level correction through the centralized buffer architecture.
Data Source
AI summary
A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input frequency; and wherein the multiple phase divider and the buffer share a same current from a supply rail.