Clock Tracking Duty Cycle Matching to Reduce Jitter and Spurs
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Solution Overview
Problem
Existing clock tracking circuits face challenges in reducing duty cycle mismatch between a reference clock and an output clock, which can lead to increased jitter and spurs.
Innovation Solution
The proposed solution involves a clock tracking circuit with a duty cycle matching circuit that compares the duty cycles of the reference and output clocks, and adjusts the duty cycle of the output clock to match the reference clock, thereby reducing duty cycle mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a clock tracking circuit is used to track the output clock to the reference clock, then the phase and frequency of the output clock are locked to the reference clock, but duty cycle mismatch between the reference clock and the output clock increases leading to increased jitter and spurs
Solution Approach 1:
The patent implements a feedback mechanism where the duty cycle of the output clock is continuously compared with the duty cycle of the reference clock. Based on this comparison, the circuit dynamically adjusts the output clock's duty cycle to match the reference clock's duty cycle, thereby eliminating duty cycle mismatch and reducing the resulting jitter and spurs while maintaining accurate phase and frequency tracking
Solution Approach 2:
The patent changes the duty cycle parameter of the output clock by adjusting its pulse width based on the comparison with the reference clock's duty cycle. This parameter adjustment is achieved through modifying the width of the output clock pulse in the phase detector circuit, which directly addresses the duty cycle mismatch problem and reduces the harmful effects of jitter and spurs
Data Source
AI summary
One or more examples relate to a method. The method may include: comparing a first value and a second value, the first value representing a duty cycle of a reference clock and the second value representing a duty cycle of an output clock generated by a clock tracking circuit to track the reference clock; setting a duty cycle of a changed clock to reduce duty cycle mismatch between the reference clock and the output clock indicated by the comparing; and providing the changed clock having set duty cycle in lieu of the one of the reference clock or the output clock.