Clock Transfer Circuit Address Control for Data Integrity
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Solution Overview
Problem
Existing clock transfer circuits face quality degradation due to data omission or duplication when transferring data between clocks of different frequencies, particularly in systems like DisplayPort, where address conflicts lead to memory address control failures, and increasing memory size to avoid frequent resets is not preferable as it increases circuit size and cost.
Innovation Solution
A clock transfer circuit with a memory, write and read address controllers, a cycle comparator, and a clock adjuster that compares the cycle or time difference of events between input and output data and adjusts the frequency of the secondary clock to maintain coincidence, thereby reducing memory address control failures and preventing data omission or duplication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address comparison and resetting is used to prevent memory address control failure, then address conflict is reduced, but data omission or duplication occurs resulting in quality degradation
Solution Approach 1:
The cycle comparator performs preliminary comparison of write and read clock cycles before address conflict occurs. By detecting cycle differences in advance and generating adjustment signals to synchronize the clocks, the system prevents address conflict before it happens, eliminating the need for address resetting and thereby preventing data omission or duplication.
Solution Approach 2:
The system establishes a feedback loop where the cycle comparator continuously monitors the relationship between write and read clock cycles, and the address controllers adjust their addressing based on comparison results. This closed-loop control maintains proper address sequencing without resetting, ensuring both reliability and data integrity.
2Loss of information
If memory size is increased to avoid frequent address resetting, then data quality is maintained, but circuit size and cost increase
Solution Approach 1:
The patent replaces the mechanical approach of increasing memory hardware size with a control system approach using clock cycle comparison and adjustment. The cycle comparator and address control logic dynamically synchronize addressing operations, eliminating the need for additional memory capacity to handle address reset scenarios, thus maintaining data quality without increasing circuit size.
3Adaptability or versatility
If Gray-code conversion and retiming is used for clock transfer, then transfer between clocks is achieved, but accumulated data is discarded or double-read resulting in quality degradation
Solution Approach 1:
Instead of using Gray-code conversion and retiming, the patent changes the approach by directly comparing clock cycle parameters and adjusting address generation based on cycle differences. This parameter-based adjustment method maintains the adaptability for transferring between different clock frequencies while preventing data loss by continuously synchronizing the read and write operations without discarding or duplicating data.
Data Source
AI summary
A clock transfer circuit receives input data synchronized with a first clock, and outputs, as output data, data synchronized with a second clock having a frequency different from that of the first clock. A write address controller is operating according to the first clock, and provides a write address to a memory. A read address controller is operating according to the second clock, and provides a read address to the memory. A cycle comparator compares the cycle of a predetermined event between the input data and the output data. Based on such a comparison result, the clock adjuster adjusts the frequency of the second clock.