Clock Transfer Circuit With Bias-Controlled Delay Compensation
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Solution Overview
Problem
High-speed clock signal distribution circuits face challenges in maintaining optimal signal transitions due to power supply voltage fluctuations, leading to increased jitter and deteriorated eye characteristics, particularly in systems using both current mode logic (CML) and complementary metal-oxide-semiconductor (CMOS) levels, where existing solutions like delay locked loops (DLLs) consume significant power and occupy large areas.
Innovation Solution
A semiconductor device with a delay compensation circuit that includes a variable delay circuit and a bias control circuit, which adjusts bias currents based on power supply voltage fluctuations to compensate for delay variations, enabling efficient conversion between CML and CMOS levels while minimizing power consumption and area occupancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay locked loop (DLL) circuit is used to compensate for delay fluctuation, then delay compensation is achieved, but the circuit occupies a large area and consumes a lot of power
Solution Approach 1:
The patent changes the operating parameters by using a current-mode delay element instead of a traditional voltage-mode DLL circuit. The delay compensation is achieved by adjusting the current parameter (first current from first power source, second current from second power source) to counteract delay fluctuations, thereby reducing power consumption and area while maintaining compensation effectiveness
Solution Approach 2:
The patent segments the power supply into multiple independent power sources (first power source and second power source) with different voltage characteristics. This segmentation allows independent control of current parameters to achieve delay compensation without requiring a complete DLL circuit, reducing both area and power consumption
2Reliability
If a delay locked loop (DLL) circuit is used to compensate for delay fluctuation, then delay compensation is achieved, but the circuit occupies a large area
Solution Approach 1:
The patent changes the operating parameters by using a current-mode delay element instead of a traditional voltage-mode DLL circuit. The delay compensation is achieved by adjusting the current parameter (first current from first power source, second current from second power source) to counteract delay fluctuations, thereby reducing power consumption and area while maintaining compensation effectiveness
Solution Approach 2:
The patent extracts only the essential delay compensation function from the complete DLL circuit. By using a simplified delay element with multiple power source control, it achieves the core compensation capability without the additional components (phase detectors, charge pumps, etc.) that occupy area in traditional DLL circuits
3Adaptability or versatility
If power supply voltage fluctuates, then the circuit adapts to varying conditions, but delay fluctuation increases causing clock signal transitions to occur at non-optimal times
Solution Approach 1:
The patent implements a feedback mechanism where the delay element's output is monitored and used to adjust the current parameters (first current and second current from different power sources). This feedback loop dynamically compensates for delay fluctuations caused by power supply voltage changes, ensuring clock signal transitions occur at optimal times despite varying power conditions
Solution Approach 2:
The patent makes the delay element dynamic by allowing real-time adjustment of current parameters from multiple power sources. The delay characteristic is no longer fixed but can be dynamically modified by changing the ratio of first current to second current, enabling adaptation to power supply fluctuations while maintaining optimal signal transition timing
Data Source
AI summary
A clock transfer circuit includes a first stage circuit configured to produce an output signal that uses a second signaling technology from an input signal that uses a first signaling technology; and a second stage circuit configured to produce a clock signal by delaying the output signal; wherein the first stage circuit includes a semiconductor device configured to compensate for delay fluctuation caused by fluctuation of power supply voltage between a first power source and a second power source.