Clock Transfer Circuit for Glitch-Free Phase-Aligned Switching
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Solution Overview
Problem
Existing clock circuits in mobile devices face power conservation challenges due to the need for phase-locked loops (PLLs) for controlled clocks, which require significant power, and switching between clocks can cause glitches and abrupt phase changes during transitions.
Innovation Solution
A clock transition circuit that detects the phase difference between a source clock and a destination clock, generating an interim clock to incrementally reduce the phase difference, allowing a smooth transition from one clock to another, thereby minimizing power consumption and phase disruptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a closely controlled clock (PLL) is used for all operations, then communication quality is improved, but power consumption increases
Solution Approach 1:
The system dynamically switches between two clock modes: PLL-based closely controlled clock for RF communication operations requiring high precision, and alternative clock for non-communication operations. This dynamic adaptation allows the system to use the power-intensive PLL only when necessary, reducing overall power consumption while maintaining communication quality.
2Use of energy by moving object
If switching between clocks is implemented to save power, then power consumption is reduced, but glitches and abrupt phase changes occur
Solution Approach 1:
Before switching from the alternative clock to the PLL clock, the system performs preliminary phase alignment by adjusting the PLL's phase to match the alternative clock's phase. This preliminary action ensures that when the clock switch occurs, there is no abrupt phase change or glitch, maintaining system stability during the transition.
Solution Approach 2:
The phase detector and phase adjustment mechanism act as intermediaries between the two clock sources. They detect the phase difference and mediate the transition by gradually aligning the phases, preventing direct abrupt switching that would cause glitches.
3Speed
If abrupt clock switching is performed, then transition speed is improved, but phase alignment problems occur
Solution Approach 1:
The system replaces mechanical or direct switching methods with an electronic phase detection and adjustment mechanism. The phase detector electronically measures the phase difference, and the phase adjustment circuit electronically modifies the PLL output phase, enabling precise phase alignment without mechanical delays or abrupt transitions.
Data Source
AI summary
An apparatus including a multiplexer configured to provide an output clock selected from a source clock, a destination clock, and a transition clock is provided. The apparatus further includes a phase difference calculation module configured to calculate a phase difference between the source clock and the destination clock and a clock generation module configured to generate a plurality of clocks. The apparatus further includes a clock selection module configured to select one of the plurality of clocks as the transition clock and a control circuit configured to provide: (1) a signal to the clock selection module for selecting one of the plurality of clocks as the transition clock based on the phase difference between the source clock and the destination clock and (2) a signal to the multiplexer to provide as the output clock one of the source clock, the destination clock, or the transition clock.