Clock Tree Multi-Mode Circuit for NBTI and PBTI Aging Control
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Solution Overview
Problem
Existing clock tree circuits in system-on-chip (SoC) experience degradation due to Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI) effects during power saving modes, leading to asymmetric aging and potential functional failures.
Innovation Solution
The implementation of a multi-mode circuit design where transistors become inactive during power saving modes, using a first signal to inactivate a first transistor and a second signal to inactivate a third transistor, thereby preventing degradation. This design includes transistor-based clock tree elements in parallel connections, with specific transistors being active during functional modes and inactive during gating modes to mitigate aging effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock gating mode is used to reduce active power, then power consumption is reduced, but transistor degradation occurs due to NBTI and PBTI effects
Solution Approach 1:
The circuit dynamically switches between functional mode and clock gating mode based on operational requirements. During clock gating mode, the circuit maintains power reduction while periodically transitioning to functional mode to refresh transistors and prevent degradation from prolonged exposure to bias conditions.
Solution Approach 2:
The circuit implements periodic switching between clock gating mode and functional mode. This periodic action allows transistors to be refreshed at intervals, preventing cumulative degradation from NBTI and PBTI effects while maintaining overall power reduction benefits.
2Speed
If transistors remain active during power saving mode, then timing performance is maintained, but asymmetric aging occurs due to NBTI and PBTI effects
Solution Approach 1:
The circuit dynamically adjusts transistor states based on mode requirements. In clock gating mode, specific transistors are deactivated to prevent asymmetric aging, while the circuit maintains timing performance through proper mode switching and signal path management.
Solution Approach 2:
The circuit changes operational parameters by switching between functional mode and clock gating mode. This parameter change allows the circuit to adjust transistor activation states, preventing asymmetric aging while maintaining acceptable timing performance through mode transitions.
3Use of energy by moving object
If clock gating is implemented to save power, then power consumption decreases, but functional failures may occur due to transistor degradation
Solution Approach 1:
The circuit proactively prevents transistor degradation by implementing periodic mode switching before significant degradation can occur. This beforehand cushioning approach refreshes transistors at intervals, preventing cumulative damage that would lead to functional failures.
Solution Approach 2:
The circuit employs periodic switching between clock gating mode and functional mode to refresh transistors before degradation reaches critical levels. This periodic maintenance approach prevents functional failures while maintaining overall power savings.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes transistor degradation across multiple operating modes, reducing timing performance issues and preventing functional failures by ensuring transistors remain non-degraded during power saving modes, thus enhancing the reliability and longevity of clock tree circuits.
Implementation Method 1
when the gating signal is at logic level LO (falling edge) then the PMOS transistor 110A is active and hence is subject to Negative Bias Temperature Instability (NBTI) effect
Implementation Method 2
at least one NMOS transistor, for example the NMOS transistor 115A, that is active when the gating signal is at logic level HI can get degraded due to a positive bias temperature instability (PBTI) effect
Data Source
AI summary
Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the circuit in a first mode. The first transistor is responsive to a first signal to become inactive when the circuit enters into a second mode, thereby preventing degradation of the first transistor when the circuit enters into the second mode. A second transistor is coupled to the first transistor. The second transistor is responsive to a second signal to generate a third signal. A third transistor is coupled to the second transistor. The third transistor is responsive to the third signal to become inactive when the circuit enters into the second mode, thereby preventing degradation of the third transistor when the circuit enters into the second mode.