Clock Tree Back Gate Potential Modulation for Low Voltage Operation
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Solution Overview
Problem
Integrated circuits face performance deterioration and increased sensitivity to voltage reductions, leading to clock skew and time constraint violations when powered with low voltage, complicating design and fabrication.
Innovation Solution
The method involves configuring clock-tree cells with specific field-effect transistors and back gate potential differences to modulate threshold voltage, increasing fan-out and maintaining transition time, even at reduced supply voltages, by using pMOS and nMOS transistors with semiconductor wells and deep wells to improve clock tree performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the power supply voltage is reduced to ultra-low voltage to reduce power consumption, then energy efficiency is improved, but the performance of the clock tree deteriorates due to greater sensitivity to transistor fabrication variability
Solution Approach 1:
The patent applies back gate potential differences to field-effect transistors in the clock tree to dynamically adjust their threshold voltages. By changing the electrical parameter (threshold voltage) of the transistors, the clock tree maintains adequate signal propagation even at ultra-low supply voltages, thus resolving the contradiction between low power consumption and reliable clock tree operation
Solution Approach 2:
The invention introduces dynamic control of transistor characteristics through adjustable back gate potentials. This allows the clock tree to adapt its performance characteristics in real-time, maintaining reliability across varying supply voltage conditions including ultra-low voltage operation, thereby resolving the contradiction between energy efficiency and performance stability
2Use of energy by moving object
If the power supply voltage is reduced to ultra-low voltage to reduce power consumption, then energy efficiency is improved, but time constraint violations increase due to greater sensitivity to fabrication variability
Solution Approach 1:
By adjusting the threshold voltage of transistors through back gate potential differences, the patent ensures that signal propagation times remain within acceptable constraints even at ultra-low supply voltages. This parameter adjustment compensates for fabrication variability effects, preventing time constraint violations while maintaining low power consumption
Solution Approach 2:
The patent applies back gate potentials in advance to pre-compensate for the increased sensitivity to fabrication variability that occurs at low voltages. This preliminary adjustment counteracts the potential for time constraint violations before they occur, allowing ultra-low voltage operation without sacrificing timing reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the robustness and performance of the clock tree under low voltage conditions, reducing the impact of voltage reductions on clock signal propagation and maintaining fan-out and transition time, thereby improving electrical performance.
Implementation Method 1
a back gate potential difference of one of the field-effect transistors is defined as a difference between an electric potential applied to a source of the field-effect transistor less an electric potential applied to a back gate of the field-effect transistor
Data Source
AI summary
A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.