Clock Tree Buffer Stuck-At Fault Detection via Scan Chain
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Solution Overview
Problem
Current automated testing systems for integrated circuit devices face challenges in detecting stuck-at fault conditions, particularly in clock tree buffers, as existing methods are inadequate for identifying such faults effectively.
Innovation Solution
A circuit design incorporating a first and second clock source, a multiplexer circuit, a non-scan flip flop, and a scan chain is employed to generate and select clock signals, allowing for the detection of stuck-at faults in buffer circuits within clock trees by capturing data outputs and using a scan chain to confirm proper operation or fault conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing testing methods are used for clock tree buffers, then the testing system remains simple, but stuck-at fault detection capability is insufficient
Solution Approach 1:
The patent introduces a scan chain as an intermediary testing mechanism between the clock tree buffers and the test output. The scan chain includes scan flip-flops that capture and serialize the output states of clock tree buffers, enabling external observation of internal buffer states without directly modifying the buffer circuits themselves. This intermediary structure enables precise fault detection while maintaining relative simplicity in the overall testing architecture.
Solution Approach 2:
The testing circuit is segmented into distinct functional components: clock sources, multiplexers for signal selection, scan flip-flops for data capture, and a scan chain for serial output. This segmentation allows each component to be optimized for its specific function while collectively achieving comprehensive fault detection capability without requiring complete redesign of the entire testing system.
2Reliability
If a scan chain is added to detect clock tree buffer faults, then fault detection accuracy improves, but the device complexity increases
Solution Approach 1:
The scan chain is designed to serve multiple functions: it captures output states from clock tree buffers, serializes the data for external observation, and can be integrated with existing scan-based testing infrastructure. The scan flip-flops used in the chain are multi-functional elements that can operate in both capture mode (for fault detection) and shift mode (for data serialization), reducing the need for separate dedicated testing components and thereby limiting the increase in overall circuit complexity.
Data Source
AI summary
A first clock signal and second clock signal are generated by first and second clock circuits, respectively. A multiplexer selects between the first clock signal and second clock signal to produce a scan clock signal. A non-scan flip flop clocks a data input through to a data output in response to the second clock signal. A scan chain includes a scan flip flop configured to capture the data output from the non-scan flip flop in response to the scan clock signal. The logic state of the captured data in the scan flip flop of the scan chain is indicative of whether the second clock circuit has a stuck-at fault condition (for example, with respect to any one or more included buffer circuits).