Clock Tree Buffering Solution Selection Using ROI Metric
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Solution Overview
Problem
In integrated circuit (IC) design, existing clock tree synthesis buffering solutions face challenges in balancing insertion delay and area tradeoffs, leading to inefficiencies in clock signal propagation and potential timing issues.
Innovation Solution
A clock delay and area-based buffering solution selection process is introduced, which uses a return on investment (ROI) metric derived from a slope approach to measure the root-pin slack versus total cell area curve, allowing for the selection of buffering solutions that optimize delay versus area tradeoffs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If buffers are inserted into the clock tree to improve delay, then insertion delay is reduced, but die area increases
Solution Approach 1:
The patent changes the parameter of buffer selection from purely delay-based to a multi-parameter optimization that includes both delay and area. By introducing an ROI metric that combines root-pin slack (delay parameter) and total cell area, the system selects buffering solutions that optimize the tradeoff between insertion delay and die area, rather than simply minimizing delay at the cost of area.
2Reliability
If multiple buffering solutions are evaluated based on delay only, then timing performance is improved, but area efficiency deteriorates
Solution Approach 1:
The patent creates a composite evaluation metric (ROI - return on investment) that combines multiple parameters (root-pin slack and total cell area) into a single figure of merit. This composite metric allows for the selection of buffering solutions that balance both timing performance and area efficiency, rather than optimizing for timing alone.
Data Source
AI summary
Aspects of the present disclosure include system, methods, and software for buffer insertions. In one example, a method includes receiving a clock signal network layout, wherein the clock signal layout comprises a clock source electrically coupled to a plurality of clock sinks via a plurality of net segments, and creating a plurality of buffering solutions, wherein each buffering solution of the plurality of buffering solutions comprises a plurality of buffers inserted on one or more net segments of plurality of net segments. The method further includes assigning each buffering solution a timing delay value and an area value, and selecting a buffering solution of the plurality of buffering solutions based on the timing delay value and the area value. The method additionally includes committing the selected buffering solution into an integrated circuit design comprising the clock signal network.