Timing-Aware Clock-Tree Clustering for Low Clock Divergence
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Solution Overview
Problem
Current integrated circuit designs face performance issues due to high clock divergence between interacting circuit elements, leading to race conditions and timing problems, as clock-tree synthesis is unaware of logic-interaction and timing requirements.
Innovation Solution
The solution involves clustering clocked storage elements based on their relative interaction levels, physically grouping them close together, and associating them with a common clock buffer to reduce clock divergence and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If clock-tree synthesis is performed without awareness of logic-interaction and timing requirements, then clock signal distribution is simplified, but clock divergence between interacting circuit elements increases causing race conditions
Solution Approach 1:
The patent performs preliminary clustering of interacting circuit elements based on logic-interaction analysis before clock-tree synthesis. By pre-identifying and grouping elements that interact logically, the subsequent clock-tree synthesis can target these clusters specifically, ensuring timing requirements are met without requiring complete redesign of the clock distribution system.
Solution Approach 2:
The patent applies different clocking strategies to different regions of the circuit based on local interaction patterns. By identifying clusters of interacting elements and applying localized clock buffering and routing optimizations to these specific regions, the system achieves improved timing reliability without uniformly increasing complexity across the entire clock-tree.
2Speed
If clock frequency is increased to improve performance, then processing speed increases, but timing budgets for internal setup and hold times are reduced
Solution Approach 1:
The patent dynamically adjusts clocking parameters such as buffer insertion points, clock gate placement, and local clock frequency scaling based on the identified interaction clusters. By changing these parameters locally within clusters rather than globally, the system can maintain higher overall clock frequencies while preserving sufficient timing budgets for critical paths.
Solution Approach 2:
The patent introduces dynamic clocking mechanisms where clock signals can be selectively enabled, disabled, or frequency-scaled for different circuit clusters based on their interaction intensity and timing requirements. This dynamic approach allows the system to optimize performance by providing higher clock frequencies where needed while maintaining timing budgets where interactions are less critical.
3Adaptability or versatility
If clocked storage elements are distributed throughout the circuit, then circuit functionality is improved, but clock divergence between interacting elements increases
Solution Approach 1:
The patent merges physically distributed clocked storage elements into logical clusters based on their interaction patterns. By grouping elements that frequently interact together and providing them with shared or closely-coordinated clock sources, the system maintains the functional benefits of distributed elements while achieving the synchronization benefits of clustered distribution.
Solution Approach 2:
The patent introduces clock buffer elements as intermediaries between the main clock source and distributed storage elements. These buffer elements are strategically placed within identified interaction clusters to locally regenerate and synchronize clock signals, reducing the impact of clock divergence caused by distributed element placement while maintaining circuit functionality.
Data Source
AI summary
An integrated circuit includes a clock-tree with a plurality of clock buffers, a plurality of clocked storage elements, and a plurality of logic circuits. Each clocked storage element has a clock input terminal connected to one of the plurality of clock buffers and a weight. Each of the logic circuits is associated with two of the plurality of clocked storage elements and is characterized as having a logic depth. The weight of each clocked storage element is equal to a sum of an inverse of a logic depth of each of the plurality of logic circuits associated therewith. A first clocked storage element which has a highest weight and is adjacent to and interacts with a second clocked storage element via one of the plurality of logic circuits. A first clock buffer provides a common clock signal to the first and second clocked storage elements.