Clock Tree Clustering via Nested Hierarchy Inputs
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Solution Overview
Problem
Existing electronic design automation (EDA) systems for generating clock trees require significant manual interaction, leading to high designer time consumption and potential adverse impacts on design quality due to manual modification of logical hierarchies and connectivity, which complicates the design flow and results in suboptimal clock tree quality.
Innovation Solution
The implementation of clock tree hierarchy inputs with nested lists and clustering constraints allows for automated guidance of clock tree routing, reducing designer time resources and enabling complex routing rules to guide the final clock tree design without excessive manual intervention, by specifying clustering intent through design objects like clock sinks or partitions and controlling signal transitions across partition group boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If manual interaction is used for clock tree generation, then designer control over logical hierarchies and connectivity is improved, but designer time consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-defining clustering constraints and hierarchy structures before the clock tree synthesis process. Designers specify partition groups and clustering rules in advance, which then automatically guide the clock tree generation algorithm, eliminating the need for manual intervention during the synthesis phase while preserving design intent.
Solution Approach 2:
The system implements self-service by enabling the clock tree synthesis tool to automatically cluster partitions and generate routing based on pre-specified constraints. The algorithm autonomously performs the clustering operation without requiring manual designer interaction, yet maintains control over logical hierarchies through the constraint-based approach.
2Adaptability or versatility
If manual modification of logical hierarchies is performed, then design flexibility is improved, but design quality deteriorates due to potential errors
Solution Approach 1:
The patent introduces an intermediary layer of clustering constraints that mediates between designer intent and automated synthesis. The constraint specification acts as an intermediary that captures design flexibility requirements while eliminating manual modification errors, translating high-level design intentions into precise routing guidance for the automated algorithm.
3Manufacturing precision
If complex routing rules are applied, then clock tree quality is improved, but automation difficulty increases
Solution Approach 1:
The patent applies segmentation by breaking down complex routing rules into discrete, manageable clustering constraints. Instead of requiring a single complex automation algorithm, the system divides the routing guidance into hierarchical partition groups with specific clustering rules, making the automation process more tractable while maintaining high clock tree quality through the cumulative effect of multiple constraint layers.
Data Source
AI summary
Systems, methods, media, and other such embodiments described herein relate to generation of clock routing trees. One embodiment involves accessing a circuit design and a clock tree hierarchy input indicating a nested list of partition or sink groups, each group of the nested list of groups comprising one or more clock tree elements of a plurality of clock tree elements from the circuit design. A routing topology associated with a source and a plurality of sinks are determined based on an ordering within the nested list of partition groups. These routing directions are used in synthesizing a clock tree for the circuit design. In additional embodiments, the clock tree hierarchy input provides clustering information, port placement for connections between partition groups of the clock tree, and parameters describing limitations or criteria for individual partition groups.