Clock Tree Optimization via Core Route Instance Relocation
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Solution Overview
Problem
Conventional clock tree wirelength reduction techniques rely on brute force approaches, which are computationally intensive and often fail to identify optimal solutions, leading to slow runtime and high resource utilization with a risk of getting stuck in local minima.
Innovation Solution
The method involves moving clock tree instances towards 'core' routes identified based on transitive fanout or wirelength thresholds, iteratively refining the clock tree by determining and validating new locations that reduce wirelength while adhering to timing-based design constraints, using a combination of terminal offsets to determine a target offset for each instance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a brute force compass-search algorithm is used to reduce wirelength, then wirelength reduction is achieved, but runtime increases significantly and computational resources are exhausted
Solution Approach 1:
The patent applies local quality by differentiating between core routes (high fanout) and non-core routes (low fanout). Instead of treating all clock instances uniformly, the method applies different relocation strategies based on local characteristics - moving instances on core routes while being more conservative with non-core routes. This localized approach reduces the search space and computational effort required.
Solution Approach 2:
The patent segments the clock tree into core routes and non-core routes based on fanout thresholds. This segmentation allows the algorithm to process different parts of the clock tree with different strategies, avoiding the need to exhaustively search all possible locations for all instances, thereby reducing runtime while maintaining wirelength reduction effectiveness.
2Length of moving object
If a brute force compass-search algorithm is used to reduce wirelength, then wirelength reduction is achieved, but computational resource utilization increases
Solution Approach 1:
The patent applies local quality by differentiating between core routes (high fanout) and non-core routes (low fanout). Instead of treating all clock instances uniformly, the method applies different relocation strategies based on local characteristics - moving instances on core routes while being more conservative with non-core routes. This localized approach reduces the search space and computational effort required.
Solution Approach 2:
The patent segments the clock tree into core routes and non-core routes based on fanout thresholds. This segmentation allows the algorithm to process different parts of the clock tree with different strategies, avoiding the need to exhaustively search all possible locations for all instances, thereby reducing runtime while maintaining wirelength reduction effectiveness.
3Loss of time
If a greedy compass-search algorithm is used to save runtime, then runtime is reduced, but the algorithm gets stuck in local minima and may not find optimal solutions
Solution Approach 1:
The patent introduces dynamic validation criteria that adapt during the relocation process. Instead of using a fixed greedy approach, the validation process dynamically assesses whether a relocation improves wirelength while satisfying timing constraints. This dynamic evaluation allows the algorithm to escape local minima by accepting certain moves that may not immediately reduce wirelength but enable future improvements.
Solution Approach 2:
The patent implements feedback through validation checks that continuously monitor timing constraints and wirelength improvements. The validation process provides feedback on whether proposed relocations are beneficial, allowing the algorithm to adjust its strategy and avoid getting stuck in local minima by learning from previous moves and their outcomes.
4Length of moving object
If clock instances are moved to reduce wirelength, then wirelength is reduced, but timing constraints (skew and slew) may be violated
Solution Approach 1:
The patent applies beforehand cushioning by performing validation checks before finalizing any relocation. The validation process proactively verifies that proposed moves will not violate timing constraints, preventing constraint violations before they occur. This preventive approach ensures that wirelength reduction does not compromise timing integrity.
Solution Approach 2:
The patent implements feedback through validation checks that continuously monitor timing constraints and wirelength improvements. The validation process provides feedback on whether proposed relocations are beneficial, allowing the algorithm to adjust its strategy and avoid getting stuck in local minima by learning from previous moves and their outcomes.
Data Source
AI summary
Aspects of the present disclosure address improved systems and methods for core-route-based clock tree wirelength reduction. A method may include accessing an integrated circuit design comprising a clock tree comprising routes that interconnect terminals of a plurality of clock tree instances. The method further includes identifying a core route in the clock tree. The method further includes determining a first offset based on a distance between the first terminal and the core route and determining a second offset based on a distance from the second terminal to the core route. The method further includes determining a target offset based on a combination of the first and second offsets and moving the clock tree instance toward the core route by the target offset.