Clock-Tree Branching for Common-Mode Fault Detection
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Solution Overview
Problem
Conventional functionally-safe (FuSa) systems require duplicated clock-trees, which are costly due to the need for balanced clock-trees across large systems, and struggle with detecting common mode faults efficiently.
Innovation Solution
Implementing a single clock-tree across the FuSa system that forks off at a sub-block boundary, using an asynchronous or synchronous reference clock to detect common mode faults, thereby simplifying clock-tree balancing and improving power/area goals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If duplicated clock-trees are deployed in functionally-safe systems, then fault detection capability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent segments the clock-tree into multiple domains (first clock domain and second clock domain) with a shared portion and separate portions. This segmentation allows the system to use a single physical clock-tree infrastructure while maintaining the functional separation needed for fault detection, thereby reducing complexity while preserving reliability.
Solution Approach 2:
The shared clock-tree portion serves multiple functions: it provides clock signals to both clock domains simultaneously and acts as a common reference for fault detection. By making the clock-tree multi-functional, the patent eliminates the need for completely separate duplicated clock-trees, reducing device complexity while maintaining fault detection capability.
2Reliability
If fully-duplicated clocks are used to avoid common mode faults, then system reliability is improved, but power consumption and area increase
Solution Approach 1:
The patent merges the clock-generation functionality into a single shared clock-tree that serves both clock domains. Instead of maintaining separate power-consuming clock-generation circuits for each domain, the system uses one shared clock-tree with branching paths, significantly reducing power consumption while maintaining the ability to detect common mode faults through the separate clock domains.
3Measurement precision
If two independent clock-trees are balanced across large systems, then fault detection accuracy is improved, but manufacturing cost and time increase
Solution Approach 1:
The patent segments the clock-tree into a shared portion and separate portions that can be independently balanced and optimized. This segmentation allows each domain to be manufactured and tuned independently for optimal fault detection accuracy, while the shared portion provides a common reference, thereby reducing manufacturing complexity and cost.
Data Source
AI summary
Various implementations described herein refer to an integrated circuit having a clock generator providing a clock signal. The integrated circuit may include a block having a block boundary, and the block receives the clock signal from the clock generator and provides the clock signal along a clock-tree. The integrated circuit may include a plurality of sub-blocks disposed within the block boundary of the block, and each sub-block of the plurality of sub-blocks receives the clock signal from within the block boundary of the block via the clock-tree, and diverges the clock signal into a first clock signal and a second clock signal from within a sub-block boundary of each sub-block.