Clock Tree Pessimism Analysis for Circuit Designs
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Solution Overview
Problem
Conventional static timing analysis in circuit designs assumes fixed delay values, which is not accurate for deep submicron technologies, leading to Common Clock Path Pessimism (CCPP) due to variations in delay across the die and wafer, resulting in overly pessimistic analysis that is computationally expensive to resolve.
Innovation Solution
The method transforms a clock network into a clock tree with nodes representing different clock signal arrival times and registers, creating CCPP groups where source and destination registers share a common ancestor node, allowing for reduced analysis time by calculating timing once per group instead of for each register pair.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional static timing analysis is performed assuming fixed delay values, then analysis is simpler and faster, but the analysis becomes overly pessimistic and inaccurate for deep submicron technologies
Solution Approach 1:
The patent segments the clock network into a clock tree structure with hierarchical levels. By dividing the analysis into segments (clock tree nodes at different levels), the method reduces the computational complexity of CCPP removal while maintaining accuracy. The segmentation allows processing of timing paths in manageable groups rather than evaluating all possible register pairs globally.
Solution Approach 2:
The patent applies partial action by performing timing analysis only for relevant path combinations within each CCPP group rather than exhaustively analyzing all possible source-destination register pairs. This partial analysis approach reduces computational effort while capturing the essential CCPP effects through the clock tree hierarchy.
2Measurement precision
If CCPP removal is performed for arbitrary clock networks using conventional methods, then timing analysis accuracy improves, but the analysis time grows exponentially with the size of the clock network
Solution Approach 1:
The patent segments the clock network into a hierarchical clock tree structure with levels and nodes. This segmentation transforms the exponential complexity problem into a polynomial-time solution by organizing registers and clock paths into manageable groups. Each node in the clock tree represents a segment that can be processed independently, reducing overall analysis time.
Solution Approach 2:
The patent performs partial CCPP removal by focusing analysis on specific CCPP groups identified through the clock tree structure, rather than attempting complete CCPP removal for all possible paths. This partial approach achieves sufficient accuracy for deep submicron technologies while avoiding exponential time growth.
3Reliability
If worst case delays are assumed for max paths and best case delays for min paths to incorporate delay variations, then On Chip Variation is accounted for, but Common Clock Path Pessimism increases
Solution Approach 1:
The patent segments registers into CCPP groups based on their position in the clock tree hierarchy. By grouping registers that share common clock paths, the method accurately accounts for delay variations within each group while avoiding double-counting of common path delays. This segmentation enables realistic delay modeling without excessive pessimism.
Solution Approach 2:
The patent applies partial CCPP removal by selectively eliminating common clock path pessimism only for paths within the same CCPP group, rather than attempting complete removal for all paths. This partial approach maintains reliability by accounting for On Chip Variation while reducing unnecessary pessimism in the timing analysis.
Data Source
AI summary
Method, computer program and system to perform timing analysis of designs containing clock networks by eliminating Common Clock Path Pessimism. The method includes transforming a clock network into a clock tree that includes nodes with different clock signal arrival times and leaf nodes representing source and destination registers. The tree is populated with information regarding the source and destination registers and the associated timing for the clock arrival signal. The method then enumerates Common Clock Path Pessimism (CCPP) groups, where any source register and any destination register in a CCPP group have the same nearest common ancestor node in the clock tree. The creation of CCPP groups enables analysis time reduction because only one timing calculation is required for the CCPP group instead of having to perform the analysis for each possible pair of registers. The method eliminates CCPP for each CCPP group and then displays the results.