Clock Tree Power Estimation at Register Transfer Level
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Solution Overview
Problem
Current power estimation tools at the register transfer level (RTL) for integrated circuit design lack accuracy, making it difficult to evaluate the impact of design changes on clock power consumption, as they do not account for the physical structure and dynamic effects of clock trees, which are built later in the design process.
Innovation Solution
A system and method for clock tree power estimation at the RTL using a physical power model generated from a reference post-layout design, allowing for accurate modeling and estimation of clock tree power consumption by incorporating topological and electrical characteristics, enabling the construction of a virtual clock tree with predictable power accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If power estimation is performed at the RTL stage, then flexibility for architectural changes to reduce power consumption is improved, but accuracy of power estimation deteriorates
Solution Approach 1:
The patent creates a virtual clock tree structure at the RTL stage that pre-models the physical characteristics and power consumption behavior of the actual clock tree. This preliminary modeling allows accurate power estimation to be performed early in the design process, enabling architects to make informed decisions about power-optimizing changes before proceeding to physical design stages.
Solution Approach 2:
The patent creates a virtual copy of the clock tree structure that replicates the essential physical characteristics and power consumption properties of the actual clock tree. This virtual model allows accurate power estimation at RTL by simulating the behavior of the physical clock tree without requiring the actual physical design to be completed first.
2Manufacturing precision
If clock tree structure is built during CTS stage after placement, then physical characteristics are accurately determined, but ability to estimate clock power impact at RTL deteriorates
Solution Approach 1:
The patent performs preliminary modeling of the clock tree's physical characteristics and power consumption behavior at the RTL stage, creating a virtual representation that captures essential properties. This allows power estimation to be performed early without waiting for the actual CTS stage, while still incorporating accurate physical modeling principles.
Solution Approach 2:
The patent introduces a virtual clock tree model as an intermediary between the RTL design and the physical clock tree. This virtual model serves as a mediator that allows power estimation at RTL by simulating the behavior of the physical clock tree, bridging the gap between early design stages and later physical design stages.
3Ease of operation
If traditional power estimation tools are used at RTL, then simplicity of estimation process is improved, but accuracy of clock power prediction deteriorates
Solution Approach 1:
The patent creates a virtual copy of the clock tree that replicates physical characteristics and power consumption properties, allowing traditional estimation tools to be used while achieving accurate clock power predictions. The virtual model maintains simplicity of use while improving accuracy.
Solution Approach 2:
The patent transforms the clock tree into a virtual representation with modified parameters that capture essential power consumption characteristics. This parameter transformation allows accurate power estimation while maintaining ease of operation with existing estimation tools.
Data Source
AI summary
Systems, methods and storage media are provided for clock tree power estimation at register transfer level. For example, a physical power model is generated based at least in part on a reference post-layout design. A clock tree is modeled at register transfer level based at least in part on the physical power model. Power estimation is performed for the modeled clock tree at the register transfer level.