Clock Tree Power Partitioning for Low-Jitter Memory Timing
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Solution Overview
Problem
High-speed semiconductor memory devices face reliability issues due to voltage fluctuations in external supply voltages, which affect clock signal generators and impact memory device robustness.
Innovation Solution
A clock input buffer circuit and divider circuit that combine externally-supplied and internally-generated voltages to mitigate voltage fluctuations, using a pair of driver circuits and a divider circuit to provide stable clock signals while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If external supply voltages are used to power clock tree circuitry, then power consumption is reduced, but voltage fluctuations and jitter affect timing precision and reliability
Solution Approach 1:
The patent segments the power supply system into two distinct parts: external supply voltages for general power needs and internally-generated clean voltages for clock tree circuitry. This segmentation allows the clock circuitry to be isolated from external voltage fluctuations while maintaining overall system power efficiency.
Solution Approach 2:
The patent introduces an internal voltage generation circuit as an intermediary between the external supply voltage and the clock tree circuitry. This intermediary generates clean, stable voltages from the external supply, filtering out jitter and fluctuations before they reach the sensitive clock circuits.
2Reliability
If internal voltages are used to power clock signal generators, then timing stability is improved, but current draw on supply voltages increases
Solution Approach 1:
The patent changes the voltage parameters dynamically by switching between different voltage sources based on the operational requirements. During clock signal generation, clean internal voltages are used; during other operations, external voltages are utilized, optimizing the balance between timing stability and power consumption.
Solution Approach 2:
The patent applies partial action by using internal clean voltages only for the specific clock tree circuitry that requires timing stability, rather than powering the entire system with internal voltages. This selective approach minimizes current draw while providing stability where needed.
3Adaptability or versatility
If external supply voltages are tied to multiple devices, then system integration is improved, but voltage fluctuations and noise increase
Solution Approach 1:
The patent extracts the clock tree circuitry from the common external voltage domain and provides it with dedicated internally-generated voltages. This extraction isolates the timing-critical circuits from the noise and fluctuations inherent in shared external power supplies used by multiple devices.
Data Source
AI summary
In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.