Clock Tree Rerouting for Constraint Violations
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Solution Overview
Problem
Conventional approaches to fixing clock tree design constraint violations in integrated circuits, such as increasing buffer strength or adding buffers, result in area and power costs, and can lead to unbalanced networks and new violations, while rerouting methods may worsen existing issues.
Innovation Solution
The method involves detecting clock tree design constraint violations and iteratively rerouting violating clock nets using adjusted parameter values that control the ratio of total route length to source-to-sink route length, generating rerouting candidates to find the optimal solution that corrects violations without increasing area or power costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buffer strength is increased to fix clock tree violations, then transition time and delay are improved, but area and power costs increase
Solution Approach 1:
The patent changes the routing parameters (total route length and source-to-sink route length) instead of changing buffer characteristics. By adjusting the route topology to achieve better length balance, the clock tree violations are fixed without modifying buffer strength, thereby avoiding additional area and power costs.
2Reliability
If buffer strength is increased to fix clock tree violations, then transition time and delay are improved, but power consumption increases
Solution Approach 1:
The patent changes the routing parameters (total route length and source-to-sink route length) instead of changing buffer characteristics. By adjusting the route topology to achieve better length balance, the clock tree violations are fixed without modifying buffer strength, thereby avoiding additional power consumption.
3Reliability
If buffers are added to fix clock tree violations, then transition time and delay are improved, but device complexity increases
Solution Approach 1:
The patent changes the routing parameters (total route length and source-to-sink route length) instead of adding buffers. By adjusting the route topology to achieve better length balance, the clock tree violations are fixed without increasing the number of buffers or complicating the clock network structure.
4Reliability
If routing is optimized to balance route lengths, then clock tree design constraint violations are fixed, but total route length may increase
Solution Approach 1:
The patent adjusts two competing parameters simultaneously: total route length and source-to-sink route length. The system finds an optimal balance where the source-to-sink length is sufficient to meet timing constraints while the total route length is minimized, accepting that some increase in total length may be necessary to achieve compliance.
Data Source
AI summary
Aspects of the present disclosure address systems and methods for fixing clock tree design constraint violations. An initial clock tree is generated. The generating of the initial clock tree comprises routing a clock net using an initial value for a parameter that controls a priority ratio between total route length and a maximum source-to-sink route length in each net of the clock tree. A violation to a clock tree design constraint is detected in the clock net in the clock tree, and based on detecting the violation, a rerouting candidate is generated by rerouting the clock net using an adjusted value for the parameter. A target clock tree is selected based on a comparison of timing characteristics of the rerouting candidate with the clock tree design constraint.