Clock Tree Root Relocation for Skew Minimization
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Solution Overview
Problem
Clock skew in circuit designs often leads to timing violations despite the creation of balanced clock trees, as existing tools fail to adequately address cross-domain clock skew and critical path timing constraints.
Innovation Solution
The method involves generating initial clock trees with programmable delay circuits and adjusting their delay values, and if timing constraints are not met, moving the clock root of the clock tree to a new location, converting single clock roots to multiple roots, or recentering clock roots to alleviate clock skew, using a processor to determine and optimize clock tree configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a balanced clock tree is created with initial placement of clock resources, then clock skew is minimized for parts of the circuit design, but clock skew timing violations still occur in some instances
Solution Approach 1:
The patent implements dynamic adjustment of clock root locations and delay values after initial clock tree creation. The system evaluates timing constraints and iteratively moves clock roots from initial positions to optimized positions, and adjusts programmable delay circuits, allowing the clock tree to adapt dynamically rather than remaining static after initial placement.
Solution Approach 2:
The patent replaces the static mechanical placement system with an optimized configuration system. Instead of relying solely on initial physical placement of clock resources, the system uses computational optimization to determine optimal clock root locations and delay values, substituting computational design for fixed mechanical arrangement.
2Adaptability or versatility
If multiple clock trees with multiple clock sources are used, then clock distribution flexibility is improved, but clock skew between multiple clock sources becomes more difficult to manage
Solution Approach 1:
The patent implements a feedback mechanism where the system evaluates timing constraints for all clock trees and identifies violations. Based on this feedback, the system iteratively adjusts clock root locations and delay values across multiple clock trees, using the timing constraint evaluation results to guide进一步优化 of the clock distribution network.
Solution Approach 2:
The patent changes key parameters of the clock tree structure, specifically the locations of clock roots and the delay values in programmable delay circuits. By adjusting these parameters iteratively based on timing constraint evaluation, the system optimizes multiple clock trees simultaneously while managing the complexity of coordinating multiple clock sources.
3Ease of manufacture
If clock root locations are fixed during initial placement, then clock tree generation is simplified, but timing constraints cannot be satisfied when clock skew violations occur
Solution Approach 1:
The patent performs preliminary action by creating an initial clock tree structure with clock roots placed at convenient locations during initial placement. This preliminary configuration provides a starting point that is easy to generate, and subsequent optimization steps refine this initial structure to meet timing constraints without requiring complete redesign.
Solution Approach 2:
The patent transforms the static clock root placement into a dynamic process where clock root locations can be moved from initial positions to optimized positions. The system evaluates timing constraints and iteratively adjusts clock root locations, allowing the structure to evolve from a simple initial configuration to an optimized final configuration that satisfies timing requirements.
Data Source
AI summary
The disclosure describes approaches for generating a clock tree for a circuit design. Initial clock trees are generated and elements are assigned to locations on an integrated circuit (IC). Each of the initial clock trees includes a clock root, a spine including the clock root, and branches connected to and extending from the spine. Each clock load is coupled to one of the branches. The clock tree further includes programmable delay circuits having initial delay values that are balanced. If the circuit design does not satisfy timing constraints, at least one clock root is moved from a respective first location to a respective second location.