Integrated Clock Tree Routing During FPGA Logic Placement
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Solution Overview
Problem
Existing processor-based systems for programmable logic devices, such as FPGAs, face challenges in obtaining a legal logic placement and clock routing solution efficiently, often resulting in long runtimes or unsatisfactory results for complex designs.
Innovation Solution
The proposed solution involves a design system that simultaneously optimizes logic placement and clock tree generation, using techniques like Lagrangian relaxation and branch-and-bound algorithms to iteratively refine clock tree candidates and constraints, ensuring feasible and efficient clock routing solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If clock tree routing is performed separately after logic placement, then routing can be completed, but runtime is excessive and wirelength is not optimized
Solution Approach 1:
The patent combines logic placement and clock tree routing into a single integrated process. The routing resource manager performs both placement and routing simultaneously, allowing clock tree candidates to be generated and evaluated during the placement phase itself, rather than as a separate subsequent step. This merging eliminates the sequential overhead and enables joint optimization of both operations.
Solution Approach 2:
The system generates clock tree candidates in advance during the placement phase, before final routing is committed. By preliminarily identifying feasible clock tree options and evaluating their wirelength characteristics during placement, the system prepares routing information ahead of time, avoiding the need for extensive post-placement routing computations.
2Manufacturing precision
If traditional separate placement and routing processes are used, then implementation is straightforward, but wirelength routing is not improved
Solution Approach 1:
The patent merges placement and routing functions into a unified resource manager that simultaneously optimizes both logic placement and clock tree routing. This integrated approach allows wirelength to be minimized by considering routing constraints during placement, rather than treating routing as a separate post-processing step that cannot optimize wirelength effectively.
Solution Approach 2:
The system dynamically adjusts placement parameters based on routing considerations. By evaluating clock tree candidate wirelength during the placement phase and using this information to guide placement decisions, the system changes the optimization parameters to jointly consider both placement quality and routing efficiency, achieving improved wirelength results.
3Reliability
If complex designs are processed with existing systems, then complete solutions can be obtained, but runtime is excessively long
Solution Approach 1:
The system performs preliminary generation of clock tree candidates during the placement phase for complex designs. By identifying and evaluating multiple clock tree options in advance, before final routing commitment, the system ensures that feasible routing solutions are found earlier in the process, reducing the overall runtime required to complete complex design implementations while maintaining solution reliability.
Solution Approach 2:
The integrated resource manager maintains continuous optimization throughout the placement and routing process. Rather than completing placement then separately performing routing, the system continuously evaluates clock tree candidates and refines both placement and routing decisions together, ensuring that useful optimization actions are performed continuously without idle transitions between separate processes.
Data Source
AI summary
Some examples described herein provide for clock tree generation for a programmable logic device, and more specifically, for clock tree generation in conjunction or simultaneous with placement of logic for a programmable logic device. In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to: generate clock trees in conjunction with placing logic for an application to be implemented in a programmable logic region of a programmable logic device; generate data routes between the placed logic; and generate a physical implementation of the application based on the placed logic, the clock trees, and the data routes. The physical implementation is capable of being loaded on the programmable logic region of the programmable logic device.