Clock Tree Routing Rules for Lower-Power Integrated Circuits
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Solution Overview
Problem
Integrated circuits face high power consumption due to continuous toggling of clock signals, which is not effectively reduced by existing technologies.
Innovation Solution
A method of routing clock trees in integrated circuits by determining the level of each clock net based on the number of clock gating cells it passes through and applying different routing rules to optimize the spacing of conductive lines, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock signal is continuously toggled to operate synchronous elements, then the circuit functionality is maintained, but power consumption increases
Solution Approach 1:
The patent applies clock gating cells to selectively enable or disable clock signals to specific clock nets based on operational requirements. Instead of continuous toggling, the clock signal is periodically activated only when needed, reducing unnecessary power consumption while maintaining circuit functionality during active periods
Solution Approach 2:
The patent implements different routing rules for clock nets at different levels, where higher-level clock nets (closer to clock source) use different spacing requirements than lower-level clock nets (closer to synchronous elements). This local differentiation optimizes power consumption by reducing capacitance and coupling effects in regions where clock signals are actively toggling
2Ease of manufacture
If uniform routing rules are applied to all clock nets, then routing simplicity is maintained, but power consumption cannot be optimized
Solution Approach 1:
The patent segments the clock distribution network into multiple hierarchical levels based on the number of clock gating cells. Clock nets are divided into first-level nets (directly from clock source), second-level nets (through one gating cell), and third-level nets (through multiple gating cells), with each level receiving appropriate routing rules to optimize power consumption
Solution Approach 2:
The patent changes routing parameters such as spacing between conductive lines based on clock net level. Higher-level clock nets use larger spacing to reduce capacitance and power consumption, while lower-level nets use smaller spacing to save area, dynamically adjusting routing characteristics to match operational needs
3Object-generated harmful factors
If larger routing space is provided for all clock nets, then coupling capacitance is reduced, but area consumption increases
Solution Approach 1:
The patent applies local quality by providing larger routing space only to clock nets that require it (higher-level nets with more toggling activity), while allowing tighter routing for lower-level nets that are gated off more frequently. This selective approach reduces coupling capacitance where necessary without unnecessarily increasing overall area consumption
Data Source
AI summary
A method of routing a clock tree including a plurality of clock nets of an integrated circuit, where each of the plurality of clock nets includes at least one clock repeater, includes determining a level of a clock net of the plurality of clock nets based on a number of clock gating cells that a clock signal passes through until the clock net receives the clock signal from a clock source and routing a plurality of conductive lines in each of the plurality of clock nets by applying different routing rules to clock nets having different levels based on the determined level. Each of the plurality of clock nets is configured to transfer the clock signal to a plurality of synchronous elements or another clock net. The plurality of synchronous elements operate in synchronization with the clock signal and are included in the integrated circuit.