Clock Tree Circuit Layout Across Stitch-Exposed Imaging Regions
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Solution Overview
Problem
The formation of a clock tree that crosses multiple circuit regions with the same circuit pattern is challenging due to delays in clock signal propagation, especially in large-area semiconductor elements manufactured using stitch exposure, where forming a unified clock tree across these regions is difficult.
Innovation Solution
A clock transmission circuit with a clock tree provided on a single substrate, utilizing circuit elements switchable between high impedance and pass states, and controlled states to form a clock tree that crosses multiple circuit regions, reducing signal delay by controlling the states of circuit elements like TRI-STATE type buffers or inverters to minimize resistance and stabilize signal levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If stitch exposure is used to manufacture large-area semiconductor elements with multiple circuit regions, then the area of the semiconductor element is increased, but the clock signal propagation delay across circuit regions worsens
Solution Approach 1:
The patent divides the large semiconductor element into multiple circuit regions (first, second, third, and fourth circuit regions) with identical circuit patterns arranged in a matrix. Each region is formed by stitch exposure using a common exposure pattern, allowing the large area to be manufactured while maintaining uniform clock tree structures within each region that can be seamlessly connected across region boundaries.
Solution Approach 2:
The patent controls the impedance states of circuit elements (such as switching between high impedance and low impedance states) to optimize clock signal propagation. By adjusting impedance parameters of specific circuit elements at region boundaries, the clock tree can be continuously configured across multiple circuit regions, reducing propagation delay while maintaining the benefits of large-area manufacturing through stitch exposure.
2Ease of manufacture
If a clock tree is formed in each circuit region independently, then the ease of formation is improved, but the ability to form a unified clock tree across regions worsens
Solution Approach 1:
The patent employs a common exposure pattern that can be reused across multiple stitch exposure operations to form identical circuit patterns in different circuit regions. This universal pattern approach allows each region to be manufactured independently with the same process, yet the resulting circuit elements can be interconnected to form a unified clock tree across all regions, achieving both ease of manufacture and cross-region adaptability.
Solution Approach 2:
While maintaining identical circuit patterns across all circuit regions for uniform manufacturing, the patent applies local control of circuit element states (such as switching specific elements between high and low impedance) to configure the clock tree topology. This local quality adjustment at boundaries enables seamless connection between regions, allowing independent region formation while achieving unified cross-region clock distribution.
3Stability of the object's composition
If circuit elements are controlled to be in high impedance state, then the signal level stability is improved, but the signal propagation speed worsens
Solution Approach 1:
The patent utilizes periodic switching of circuit elements between high impedance and low impedance states to propagate clock signals through the clock tree. By rhythmically changing the impedance state of circuit elements along the signal path, the system achieves both signal level stability (when in high impedance state) and signal propagation speed (when switched to low impedance state), optimizing both parameters through time-dependent control.
Data Source
AI summary
A clock transmission circuit includes a plurality of circuit regions that have common circuit patterns and are arranged along one direction. Each of the circuit patterns of the plurality of circuit regions has at least two circuit elements that are switchable between a high impedance state and a pass state, and wirings that are connected to the circuit patterns of circuit regions adjacent to concerned circuit region, among the plurality of circuit regions. States of the at least two circuit elements of the plurality of circuit regions are controlled to be predetermined states determined for each circuit region, so that at least a part of a clock tree crossing the plurality of circuit regions is configured.