Clock Tree Input Control for Low-Power Transistor Stress Balancing
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Solution Overview
Problem
In semiconductor apparatuses operating in low power modes, the clock distribution network experiences uneven transistor deterioration due to continuous stress on specific transistors when the input signal is fixed to a specific logic level, leading to performance degradation and issues like duty error, phase mismatch, and delay mismatch.
Innovation Solution
A clock distribution network incorporating an input control circuit that alternately changes the DC level of the control input clock signal whenever the low power mode signal is enabled, mitigating uneven transistor stress by alternating the logic levels of the clock signals across the clock tree buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the input signal is fixed to a specific logic level to reduce power consumption in low power mode, then power consumption is reduced, but specific transistors receive continuous stress causing uneven deterioration
Solution Approach 1:
The patent applies periodic action by alternately changing the DC level of the control input clock signal between first and second levels each time the low power mode signal is enabled. This periodic switching prevents continuous stress on specific transistors by distributing the stress evenly across different transistor groups over time, while still maintaining low power consumption during low power mode operation.
2Use of energy by moving object
If the input signal is fixed to a specific logic level to deactivate the clock distribution network, then power consumption is reduced, but duty error, phase mismatch, and delay mismatch occur
Solution Approach 1:
The periodic switching of DC levels in the control input clock signal ensures that clock tree buffers remain periodically active rather than completely deactivated. This maintains their operational characteristics and prevents duty error, phase mismatch, and delay mismatch that would occur with complete deactivation, while still achieving power reduction during low power mode.
Solution Approach 2:
The patent changes the DC level parameter of the control input clock signal between two distinct levels (first level and second level) instead of fixing it to a single level. This parameter change allows the clock distribution network to maintain its functional characteristics and prevent timing errors while still operating in a low power state.
Data Source
AI summary
A clock distribution network includes an input control circuit and a clock tree. The input control circuit is configured to generate a control input clock signal based on an input clock signal and a low power mode signal. The clock tree is configured to generate an output clock signal by buffering the control input clock signal. When the low power mode signal is enabled, the input control circuit is configured to change a DC level of the control input clock signal.