Automated Global Clock Tree Synthesis Across Physical Hierarchies
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Solution Overview
Problem
Designing a balanced global clock tree across multiple physical hierarchies in complex integrated circuits is challenging due to the need for manual stitching and sub-optimal quality of results, with existing automated solutions unable to create symmetric trees and manage routing blockages effectively.
Innovation Solution
An automated method for building a global clock tree that inserts clock drivers at symmetric locations across multiple hierarchy levels, generates routes while matching wire lengths, and provides top-level visibility into block-level routing blockages, allowing for optimized and balanced clock tree synthesis across physical hierarchies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If manual stitching is used to build clock tree across physical hierarchies, then flexibility in routing is improved, but design complexity and time consumption increase significantly
Solution Approach 1:
The system performs self-service by automatically generating clock tree routes across physical hierarchies without requiring manual stitching. The automated routing engine navigates through block boundaries and adjusts routes dynamically, eliminating the need for manual intervention while maintaining routing flexibility through algorithmic decision-making.
Solution Approach 2:
The clock tree synthesis tool achieves universality by handling multiple functions: automatic driver insertion, cross-hierarchy routing, wire length matching, and block boundary navigation. This multi-functional approach replaces multiple manual operations with a single automated system that manages the entire clock tree construction process across hierarchical boundaries.
2Productivity
If automated clock tree synthesis is implemented, then productivity is improved, but ability to create symmetric trees and manage routing blockages deteriorates
Solution Approach 1:
The system implements feedback mechanisms by continuously monitoring wire lengths of symmetric routes and adjusting routing decisions to maintain balance. The automated synthesis tool compares wire lengths of opposing clock tree branches and modifies routes dynamically to achieve symmetry, ensuring that productivity gains do not compromise precision requirements.
Solution Approach 2:
The system strategically applies asymmetry by allowing asymmetric routing at block boundaries when necessary, while maintaining overall symmetry at the global clock tree level. This selective asymmetry enables the automated tool to navigate physical hierarchy constraints while preserving the required symmetry for timing balance through compensatory routing adjustments.
3Stability of the object's composition
If clock drivers are inserted at symmetric locations across multiple hierarchy levels, then clock distribution balance is improved, but routing complexity increases
Solution Approach 1:
The system applies segmentation by dividing the clock tree construction into discrete hierarchical levels and inserting clock drivers at symmetric locations within each level. This segmented approach maintains distribution balance by ensuring symmetry at each hierarchy level while the automated routing engine manages the complexity of connecting these segmented sections across block boundaries.
4Manufacturing precision
If top-level visibility into block-level routing blockages is provided, then routing optimization is improved, but computational overhead increases
Solution Approach 1:
The system performs preliminary action by pre-identifying routing blockages at the block level before attempting to route clock tree connections. This advance knowledge allows the automated synthesis tool to plan optimal routes that avoid blockages, improving routing optimization while managing computational overhead through efficient pre-processing of block-level routing constraints.
Data Source
AI summary
Embodiments provide for building a global clock tree. In embodiments, an example method includes inserting clock drivers at symmetric locations in one or more hierarchy levels of a plurality of hierarchy levels of an integrated circuit (IC) design. The example method further includes generating one or more routes by routing one or more nets within or across the one or more hierarchy levels of the plurality of hierarchy levels. The example method further includes matching symmetric routes of the one or more routes at each of the one or more hierarchy levels irrespective of a number of physical hierarchies each associated net spans. The example method further includes placing one or more ports at one or more signal entry points where routes of the one or more routes cross physical hierarchy blocks.