Symmetrical Clock-Tree Synthesis with Pseudo Sinks
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Solution Overview
Problem
Current clock-tree synthesis techniques face challenges in achieving high accuracy and efficiency, particularly in high-speed chip designs, where clock skew and process variation complicate the optimization of clock-tree structures, often requiring lengthy simulation techniques or inaccurate timing models.
Innovation Solution
A method for synthesizing a symmetrical clock-tree structure that routes the clock source to sinks based on a predetermined fan-out constraint, using pseudo sinks and recursive TRR extensions to minimize cluster diameters and ensure equal branch lengths, thereby reducing clock skew and improving process variation tolerance without relying on simulation techniques or timing models.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If simulation techniques are used to estimate clock skew, then measurement precision is improved, but productivity deteriorates due to lengthy synthesis time
Solution Approach 1:
The patent replaces expensive, time-consuming simulation techniques with a lightweight analytical model based on timing equations. This model provides sufficient accuracy for clock skew estimation without the computational overhead of simulation, enabling fast synthesis suitable for iterative design processes.
Solution Approach 2:
The patent substitutes the mechanical simulation process with an analytical calculation system. By using closed-form timing equations and mathematical optimization, the system achieves clock skew estimation without requiring actual simulation execution, dramatically reducing computation time.
2Productivity
If compact timing models are used to speed up synthesizing, then productivity is improved, but measurement precision deteriorates due to severe clock skew
Solution Approach 1:
The patent changes the parameters of the timing model by incorporating process variation parameters (mean and sigma) into the timing equations. This allows the model to account for manufacturing variations while maintaining computational efficiency, achieving both speed and accuracy.
Solution Approach 2:
The patent segments the timing analysis into distinct components: nominal timing calculation, process variation modeling, and clock skew optimization. Each segment is handled by appropriate mathematical models, allowing the system to maintain accuracy while managing complexity efficiently.
3Measurement precision
If timing models with higher accuracy are used, then measurement precision is improved, but productivity deteriorates due to longer synthesizing time
Solution Approach 1:
The patent applies partial action by using a simplified timing model that captures the essential factors for clock skew estimation without including all the details of full-accuracy simulation. This partial model provides sufficient precision for optimization while maintaining fast computation for iterative design.
4Reliability
If process variation is taken into consideration, then reliability is improved, but device complexity increases making optimization more difficult
Solution Approach 1:
The patent incorporates process variation by adding sigma (standard deviation) as a parameter to the timing model. This allows the optimization algorithm to consider process variation effects while maintaining the same mathematical framework, avoiding increased complexity in the optimization process.
Solution Approach 2:
The patent creates a universal timing model that handles both nominal timing and process variation simultaneously. The same mathematical equations and optimization algorithms work for both cases, making the system multi-functional without increasing complexity.
Data Source
AI summary
A method for synthesizing a clock-tree structure may be applied to a physical design such as an integrated circuit or a printed circuit board to form a symmetrical clock-tree structure, while achieving the effects including minimizing a clock skew, having a process variation tolerance and increasing the synthesizing rate. To prevent a certain level from having too many branches and ensure that the clock-tree structure satisfies the fan-out constraint, a plurality of pseudo sinks are provided such that the result of factorizing the value of the number of the total sinks may satisfy the fan-out constraint. The levels in the clock-tree structure may have equal branch lengths by employing snaking routing, so as to achieve a symmetrical clock-tree structure design and reduce the clock skew of the clock-tree.