Clock Tree Synthesis Scaled-Load Clustering
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Solution Overview
Problem
Conventional clock tree synthesis techniques face challenges in load balancing, leading to power consumption issues, design rule violations, and inefficiencies in clustering due to neglecting wire capacitance and cluster span impacts.
Innovation Solution
A clock tree synthesis tool performs load-balanced clustering using a scaled cluster load, applying a cluster-span based scaling factor to balance loads recursively, thereby penalizing large cluster spans and ensuring design rule compliance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If geometry-based clustering is used to group sinks into clusters with approximately equal spans, then the clock tree structure is simplified, but power consumption increases and the number of clusters becomes large
Solution Approach 1:
The patent changes the clustering parameter from geometry-based (equal spans) to load-based (equal loads considering wire capacitance). This parameter change allows clusters to be formed based on electrical load characteristics rather than physical dimensions, resulting in fewer clusters with more sinks per cluster, thereby reducing power consumption while maintaining structural simplicity
Solution Approach 2:
The patent applies local quality by considering the specific electrical characteristics (capacitance, load) of each region when forming clusters, rather than applying a uniform geometric criterion. This allows each cluster to be optimized for its local electrical properties, reducing overall power consumption
2Use of energy by stationary object
If load-based clustering is used to group sinks into clusters with approximately equal loads, then power consumption is reduced, but clusters have large spans that violate slew and skew constraints
Solution Approach 1:
The patent introduces a scaling factor that transforms the load calculation to account for wire capacitance and cluster span effects. By changing the load parameter definition to include these factors, the clustering process simultaneously optimizes power consumption while preventing excessive cluster spans that would violate slew and skew constraints
Solution Approach 2:
The patent incorporates feedback by using a scaling factor that reflects the impact of cluster span on signal integrity. This feedback mechanism allows the clustering algorithm to adjust cluster formation to maintain slew and skew constraints while still achieving power consumption reduction through load-based grouping
3Productivity
If conventional load-based clustering is used without accounting for wire capacitance, then clustering is simpler and faster, but design rule violations occur due to large cluster spans
Solution Approach 1:
The patent modifies the load parameter to include wire capacitance effects through a scaling factor, rather than using simple pin capacitance. This parameter enhancement maintains the efficiency of load-based clustering while ensuring design rule compliance by accounting for the actual electrical characteristics affecting slew and skew
Data Source
AI summary
Aspects of the present disclosure address improved systems and methods for designing an integrated circuit design clock tree structure with scaled-load balanced clusters. Consistent with some embodiments, the system may include a clock tree synthesis (CTS) tool configured to recursively group pins to form a set of clusters that are balanced according to a scaled load. During the recursive grouping, the CTS tool scales actual loads of clusters in accordance with a scaling factor that is based on the radius of the cluster. In this way, the scaling factor penalizes large cluster spans during recursive clustering, thereby producing a clock tree structure that meets design rule constraints.