Clock Tree Synthesis Pin Insertion Delay Skew Window Adjustment
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Solution Overview
Problem
Conventional clock tree synthesis methods fail to effectively honor pin insertion delay (PID) in integrated circuit design, leading to diminished or negated useful skew due to large skew windows that do not account for skew offsets, resulting in suboptimal clock arrival times.
Innovation Solution
Dynamically adjusting the skew window for each clock sink based on a scale factor or shift factor to ensure that the clock path delay aligns with the intended pin insertion delay, thereby improving the honoring of PID during clock tree synthesis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a fixed skew window is determined during clock tree synthesis, then clock balancing is achieved within the skew window, but the pin insertion delay cannot be effectively honored due to the large skew window size
Solution Approach 1:
The skew window is dynamically adjusted based on the pin insertion delay value. Instead of using a fixed skew window determined solely by the clock skew target, the method modifies the skew window to account for the PID, thereby adapting the clock tree synthesis process to honor the intended useful skew while maintaining clock balancing within the adjusted window.
2Ease of operation
If the skew window is large to accommodate clock skew variations, then clock sinks can be buffered within the skew window, but the useful skew introduced by pin insertion delay is diminished or negated
Solution Approach 1:
The skew window adjustment is applied locally to specific clock sinks based on their individual pin insertion delay values. Each clock sink's skew window is customized to reflect its intended useful skew, allowing the system to maintain flexibility in clock tree synthesis while ensuring that each sink receives the precise useful skew it requires.
Data Source
AI summary
Aspects of the present disclosure address systems and methods for dynamically adjusting skew windows during clock tree synthesis (CTS). A method may include identifying a pin insertion delay (PID) assigned to a clock sink in a set of clock sinks of a buffer tree in an integrated circuit design. The method further includes determining a skew window for the clock sink based on a skew target and adjusting the skew window based on identifying the PID assigned to the clock sink. The skew window is adjusted based on a skew adjustment parameter. The method further includes building a clock tree based on the buffer tree and the adjusted skew window. The building of the clock tree comprises tuning a clock path delay of the clock sink according to the adjusted skew window. A layout instance may be generated for the IC design based in part on the clock tree.