Clock Tree Synthesis Timing Optimization
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Solution Overview
Problem
Conventional clock tree synthesis techniques face difficulties in optimizing timing due to restricted skewing options after initial placement, often resulting in sub-optimal placements that fail to meet timing constraints, particularly due to the challenge of zero skew constraints.
Innovation Solution
The method involves a clock tree synthesis tool that analyzes timing paths, sets clock latencies at start and end points based on delay comparisons, and outputs timing constraints to control the clock tree synthesis process, allowing for active skewing to improve timing by adjusting clock latencies and inserting additional clock latency commands into the design process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional clock tree synthesis techniques are used with initial placement, then placement is performed, but skewing options are restricted and timing optimization is limited
Solution Approach 1:
The patent applies preliminary action by performing placement without zero skew constraints first, allowing the placement tool to optimize cell positions based on other timing parameters. After placement is complete, the clock tree synthesis tool then applies skewing adjustments to meet timing requirements. This reverses the conventional sequence where zero skew constraints are applied during placement, thereby freeing up skewing options while maintaining timing precision.
2Ease of manufacture
If zero skew constraints are applied during placement, then placement is performed, but the placement and any modified placement may be sub-optimal
Solution Approach 1:
The patent extracts the zero skew constraint from the placement process, allowing placement to proceed without this restrictive constraint. The skewing functionality is then separated and applied independently by the clock tree synthesis tool after placement is complete. This separation enables the placement tool to focus on optimizing cell positions based on area and connectivity, while timing skew is handled separately, resulting in improved placement quality.
3Manufacturing precision
If skewing is applied after initial placement, then timing optimization is attempted, but options are restricted
Solution Approach 1:
The patent inverts the conventional approach by removing skewing constraints before placement rather than applying them after. This allows the placement tool to operate with maximum flexibility, and then the clock tree synthesis tool applies appropriate skewing adjustments. This inversion fundamentally changes the workflow to preserve skewing flexibility while achieving timing optimization.
Data Source
AI summary
A method of operating a computer to generate a timing constraints file for controlling a clock tree synthesis tool, the method comprising: inputting into the computer data defining a circuit to be synthesised, the circuit including a plurality of timing paths each including at least one of a first timing portion, a second timing portion and a third timing portion; executing a tool in the computer to read the data and to analyse the delay on each the first and third portion of each the timing path, to compare the delays and to set a clock latency for at least one of start and end points of the second portion of at least one timing path in dependence on the comparison; and outputting a timing constraints file including commands for controlling the clock tree synthesis tool, the commands defining the clock latencies.