Clock-Tree Generation Using Timing Criticality Clustering
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Solution Overview
Problem
Designing clock-trees for integrated circuit (IC) chips is challenging due to increasing clock frequencies, which lead to minimal timing budgets and significant challenges from on-chip variations (OCV) such as manufacturing, voltage, and temperature variations, causing clock skew and uncertainty in clock arrival times, and existing solutions like cross links and sequential merging of registers suffer from increased power consumption and unbalanced tree topologies.
Innovation Solution
A method that generates a clock-tree by creating a timing criticality profile, clustering registers based on this profile, and using commonly-shared clock paths to provide clock signals to timing critical register pairs, while applying geometric and timing constraints to ensure optimal clock-tree structure and minimize OCV impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cross links are inserted into a clock-tree structure to reduce OCV effects, then OCV tolerance is improved, but routing resources and power consumption increase significantly
Solution Approach 1:
The invention divides the clock-tree into multiple levels (leaf-level clusters and non-leaf level clusters) with selective cross links. Instead of adding cross links throughout the entire clock-tree, the method segments the tree and inserts cross links only at appropriate levels, reducing the total number of cross links needed while maintaining OCV tolerance.
Solution Approach 2:
The invention applies cross links locally only where timing criticality requires it. By analyzing timing criticality profiles and inserting cross links specifically at critical paths rather than uniformly across the clock-tree, the solution reduces unnecessary routing resources and power consumption while maintaining reliability where needed.
2Reliability
If cross links are inserted to increase clock-path sharing between registers, then OCV tolerance is improved, but the number of wires increases significantly
Solution Approach 1:
The clock-tree is segmented into hierarchical levels with cross links inserted only where necessary. Leaf-level clusters are formed first, then non-leaf level clusters are created by grouping leaf-level clusters. This segmentation allows cross links to be inserted selectively at non-leaf levels rather than between all register pairs, reducing wire count.
Solution Approach 2:
Instead of adding cross links between all possible register pairs (excessive action), the invention adds cross links only where timing criticality analysis indicates they are needed (partial action). This selective approach reduces the number of wires while maintaining sufficient OCV tolerance.
3Reliability
If sequential merging of timing-critical register pairs is performed without physical proximity information, then OCV tolerance is improved, but tree topology becomes unbalanced and wire length overhead increases
Solution Approach 1:
The invention incorporates physical proximity information into the clustering process by considering the spatial locations of registers when forming leaf-level clusters. This local awareness ensures that clustered registers are physically close to each other, minimizing wire length while maintaining timing criticality-based OCV tolerance.
Solution Approach 2:
The invention adds the spatial dimension to the clustering process by considering both timing criticality and physical proximity. Instead of merging registers based solely on timing criteria, the method evaluates registers in the spatial domain as well, forming clusters that are both timing-critical and physically compact, thereby reducing wire length.
Data Source
AI summary
One embodiment of the present invention relates to a process that generates a clock-tree on an integrated circuit (IC) chip. During operation, the process starts by receiving a placement for a chip layout, where the placement includes a set of registers at fixed locations in the chip layout. The process then generates a timing criticality profile for the set of registers, wherein the timing criticality profile specifies timing criticalities between pairs of registers in the set of registers. Next, the process clusters the set of registers based on the timing criticality profile to create a clock-tree for the set of registers. By clustering the registers based on the timing criticality profile, the process facilitates using commonly-shared clock paths in the clock-tree to provide clock signals to timing critical register pairs.