Clock Tree Voltage Partitioning for Stable Memory Timing

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Solution Overview

Problem

High-speed semiconductor memory devices face reliability issues due to voltage fluctuations in external supply voltages, which affect clock signal timing and noise sensitivity, particularly in clock signal generators, leading to potential memory device instability.

Innovation Solution

A semiconductor device design incorporating a clock input buffer and divider circuitry that combines externally-supplied and internally-generated voltages to mitigate voltage fluctuations, using a pair of driver circuits and a divider circuit to generate stable clock signals, where the clock input buffer receives complementary clock signals and provides internal clock signals based on both external and internal voltages, while the divider circuit generates divided clock signals using internal and external voltages to reduce power consumption and jitter.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If external supply voltages are used to power clock signal generators, then power consumption is reduced, but voltage fluctuations and noise affect clock signal timing and reliability

Engineering Contradiction:

Improvepower consumptionVSAvoidclock signal timing stability

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The power supply system is segmented into two independent paths: one for generating internal voltages (using external supply) and another for driving clock circuits (using internal voltages). This segmentation isolates the clock signal generators from external voltage fluctuations while maintaining power efficiency through shared voltage generation infrastructure.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Internally-generated voltages act as an intermediary between external supply voltages and clock signal generators. The voltage generation circuit converts external supply voltages into stable internal voltages that are then used to power clock circuits, buffering them from external noise and fluctuations.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If internal voltages are used to power clock signal generators, then voltage stability and noise immunity are improved, but power consumption increases

Engineering Contradiction:

Improveclock signal timing stabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent merges the voltage generation function with the power distribution system. A single voltage generation circuit serves dual purposes: generating internal voltages for noise-sensitive clock circuits and providing power to other device components, thereby reducing overall power consumption while maintaining stability where needed.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Different quality levels of power supply are applied locally: high-stability internal voltages are used specifically for clock signal generators that require noise immunity, while other less sensitive circuits can tolerate direct connection to external supply voltages, optimizing the balance between stability and power consumption.

Inventive Principle:

Principle #3Local quality

3Device complexity

If external supply voltages are directly connected to clock circuits, then device complexity is reduced, but clock signals become sensitive to voltage jitter and fluctuations

Engineering Contradiction:

Improvevoltage generation circuitryVSAvoidvoltage fluctuations impact

Core Design Contradiction:

Device complexityVSObject-affected harmful factors

Solution Approach 1:

The harmful aspect of external supply voltages (noise and fluctuations) is extracted and separated from the clock circuit power supply. The voltage generation circuit extracts only the necessary power while filtering out harmful fluctuations, providing clean internal voltages to clock circuits.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The voltage generation circuit provides beforehand cushioning by pre-converting external supply voltages into stable internal voltages before they reach the clock circuits. This protective conversion happens in advance, cushioning the sensitive clock circuits from voltage jitter and fluctuations.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS11132015B2Powering clock tree circuitry using internal voltages

Publication Date: 2021.09.28 MICRON TECHNOLOGY INC

AI summary

In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.