Clock Trigger Circuit for Race-Free Low-Voltage Operation
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, they face challenges with decreasing operating voltages, leading to susceptibility to process, voltage, and temperature (PVT) variations, race conditions, and limited immunity to clock slew variations, which affect their performance.
Innovation Solution
The implementation of a clock circuit with a clock trigger circuit that controls both the latch and trigger circuits using a single clock enable path, providing better immunity to PVT variations and allowing a larger range of operating voltages, while also incorporating a level shifter circuit for dual-rail memory designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional clock circuits are used with decreasing operating voltages, then device complexity is reduced, but reliability deteriorates due to susceptibility to PVT variations and race conditions
Solution Approach 1:
The patent merges the clock enable path control into a unified structure where a single clock enable signal simultaneously controls both the latch circuit and trigger circuit. This consolidation reduces the number of separate control paths while ensuring synchronized operation, thereby improving reliability against PVT variations without significantly increasing device complexity
Solution Approach 2:
The clock enable path is designed to serve multiple functions: it enables the latch circuit, triggers the trigger circuit, and coordinates the overall clock circuit operation. This multi-functional design reduces the need for separate control mechanisms, maintaining low device complexity while enhancing reliability through coordinated control
2Device complexity
If traditional clock circuits are used, then device complexity is low, but race conditions occur due to limited immunity to clock slew variations
Solution Approach 1:
By merging the control of latch and trigger circuits under a single clock enable path, the patent ensures that both circuits are activated and deactivated simultaneously. This eliminates timing mismatches that could lead to race conditions, while the integrated design keeps the circuit structure relatively simple
3Reliability
If a single clock enable path is used to control latch and trigger circuits, then immunity to PVT variations improves, but device complexity increases
Solution Approach 1:
The single clock enable path is designed as a universal control mechanism that simultaneously manages the latch circuit, trigger circuit, and overall clock circuit operation. This multi-functional approach improves immunity to PVT variations by ensuring synchronized control while avoiding the need for multiple separate control circuits, thereby limiting the increase in device complexity
Data Source
AI summary
A clock circuit includes a first latch circuit, second latch circuit, first trigger circuit and second trigger circuit. The first latch circuit is configured to generate a first latch output signal based on at least a trigger signal or an output clock signal. The second latch circuit is coupled to the first latch circuit, and configured to generate the output clock signal responsive to a control signal. The first trigger circuit is coupled to the second latch circuit, and configured to adjust the output clock signal responsive to at least the first latch output signal. The second trigger circuit is coupled to the first latch circuit and the first trigger circuit by a first node, configured to generate the trigger signal responsive to an input clock signal, and configured to control the first latch circuit and the first trigger circuit based on at least the trigger signal.