Clock Trigger Circuit for Race-Free Wide-Voltage Clock Generation
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, they face challenges with decreasing operating voltages, leading to susceptibility to process, voltage, and temperature (PVT) variations, clock slew variations, and limited operating voltage ranges in clock circuits.
Innovation Solution
The implementation of a clock circuit design that uses a clock trigger circuit to control both the latch and trigger circuits via a single clock enable path, providing immunity to PVT variations, race-free operation over a larger range of conditions, and supporting a wider range of operating voltages through the integration of a level shifter circuit for dual-rail memory designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional clock circuit designs are used, then the circuit can operate at basic functionality, but the circuit becomes susceptible to PVT variations and has limited operating voltage range
Solution Approach 1:
The patent implements dynamic control of the clock enable path using a trigger circuit that responds to clock signal transitions. The trigger circuit dynamically adjusts the timing and duration of latch enable signals based on actual clock edge detection, allowing the circuit to adapt to varying PVT conditions and maintain reliable operation across a wider voltage range.
Solution Approach 2:
The patent changes the operational parameters of the latch circuit by introducing controlled enable periods that are synchronized to clock edges. By dynamically adjusting when the latch is enabled and disabled based on trigger circuit output, the circuit achieves improved immunity to PVT variations while expanding the usable operating voltage range beyond traditional fixed-enable designs.
2Ease of operation
If multiple control paths are used for latch and trigger circuits, then each circuit can be independently controlled, but race conditions may occur and operation becomes complex
Solution Approach 1:
The patent merges the control of the latch circuit and trigger circuit into a single unified clock enable path. The trigger circuit generates an enable signal that simultaneously controls both the latch and ensures proper triggering, eliminating race conditions that would otherwise occur with independent control paths while maintaining coordinated operation of both circuits.
Solution Approach 2:
The trigger circuit incorporates feedback from the clock signal and latch output to dynamically control the enable period. This feedback mechanism ensures that the latch is enabled only during the appropriate clock edge transition, preventing race conditions between the trigger and latch circuits while simplifying the overall control logic through unified timing control.
3Volume of moving object
If operating voltage is decreased to scale down IC size, then device density increases, but the circuit becomes more susceptible to PVT variations
Solution Approach 1:
The patent employs dynamic timing control that adapts to lower operating voltages by extending the latch enable period relative to the clock cycle. This dynamic adjustment compensates for slower signal propagation at reduced voltages, maintaining reliable operation despite the increased susceptibility to PVT variations that comes with scaled-down device dimensions.
Solution Approach 2:
The patent changes the temporal parameters of the clocking operation by introducing a controlled enable window that is synchronized to clock edges and adjusted for lower voltage operation. This parameter change allows the circuit to maintain proper timing margins and reliability even when operating at reduced voltages enabled by IC scaling.
Data Source
AI summary
A clock circuit includes a first latch, second latch, first trigger circuit and clock trigger circuit. The first latch generates a first latch output signal based on a first control signal, an enable signal and an output clock signal. The second latch is coupled to the first latch, and configured to generate the output clock signal responsive to a second control signal. The first trigger circuit is coupled to the first latch and the second latch, and configured to adjust the output clock signal responsive to at least the first latch output signal or a reset signal. The clock trigger circuit is coupled to the first latch and the first trigger circuit by a first node, is configured to generate the first control signal responsive to an input clock signal, and configured to control the first latch and the first trigger circuit based on at least the first control signal.