Multi-Phase Clock Trim Circuit for Quadrature Error Correction
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Solution Overview
Problem
Memory devices experience errors in clock signals due to device variation and power supply mismatch, leading to quadrature errors that affect proper operation and data transfer.
Innovation Solution
A trim circuit is employed to perform phase tuning, adjusting the phase-to-phase alignment of multiple divided clock signals to reduce or eliminate quadrature errors, using per-phase and two-phase tuning methods based on the nature of the error.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a divided multi-phase clocking scheme is used to divide a full frequency clock signal into multiple lower frequency clock signals, then the clock signals can be propagated more easily within timing requirements, but quadrature errors occur due to device variation and power supply mismatch
Solution Approach 1:
The patent implements feedback mechanisms through trim circuits that continuously monitor and adjust the phase of divided clock signals. The system measures the actual phase differences between clock signals and feeds this information back to delay elements that compensate for deviations, thereby maintaining accurate quadrature relationships despite device variations and power supply mismatches.
Solution Approach 2:
The patent changes the delay parameter of clock signals dynamically through trim circuits. By adjusting the delay amount of individual phase signals, the system compensates for phase errors caused by device variation and power supply mismatch, transforming the fixed phase relationship into an adjustable one that can be optimized for accuracy.
2Adaptability or versatility
If device variation and power supply mismatch occur in memory devices, then manufacturing costs are reduced and device diversity is increased, but quadrature errors are introduced that affect proper operation
Solution Approach 1:
The patent applies local quality by implementing separate trim circuits for each phase of the multi-phase clock signal. Each trim circuit independently adjusts the delay of its associated phase signal, allowing localized compensation for phase errors. This per-phase adjustment capability enables the system to handle device variations and power supply mismatches that affect different phases differently, maintaining overall clock accuracy despite component tolerances.
Data Source
AI summary
Systems and methods are provided for generating timing control signals for phase and duty cycle trimming to reduce or eliminate a quadrature error of a clock signal in a memory device. The memory device employs a trim circuit to perform phase tuning to reduce or eliminate the quadrature error. Different phase tuning settings are used by the trim circuit for different types of quadrature errors. The trim circuit adjusts different phases of the clock signal independently or dependently based on the phase tuning settings.