Clock Ungating Frequency Ramping for Voltage Droop Mitigation
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Solution Overview
Problem
High-speed digital electronics experience voltage droop due to fast clock signal frequency changes, leading to increased power consumption and degraded circuit performance, particularly when clock signals are quickly re-enabled after being gated.
Innovation Solution
A voltage droop mitigation circuit that modulates the clock frequency over a controlled time period using programmable mask patterns or Boolean functions, reducing the abruptness of clock ungating and minimizing voltage droop by selectively controlling clock signal assertion across multiple processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock signals are quickly re-enabled after being gated to restore full performance, then circuit performance is improved, but voltage droop increases
Solution Approach 1:
The patent applies preliminary action by gradually ramping up the clock frequency before full operation is needed. When a processor core exits idle state, the clock frequency is incrementally increased through multiple stages rather than immediately restored to full frequency, allowing the power delivery network to stabilize and avoid voltage droop while still restoring performance.
Solution Approach 2:
The patent implements dynamics by making the clock frequency adaptive and variable during the wake-up process. The frequency transitions from zero to maximum through dynamically controlled intermediate stages, with each stage's duration and frequency value adjusted based on real-time voltage monitoring and system state, optimizing both performance restoration and voltage stability.
2Loss of energy
If clock frequency is rapidly increased upon ungating, then power consumption is reduced, but voltage droop and power consumption spikes increase
Solution Approach 1:
The patent applies periodic action by dividing the clock frequency restoration into discrete time stages with periodic transitions. The clock frequency progresses through predefined frequency levels at controlled intervals, with each transition synchronized to allow power delivery network stabilization, thereby reducing energy loss from voltage droop while maintaining efficient power consumption.
3Object-affected harmful factors
If clock frequency is gradually ramped up, then voltage droop is reduced, but time to restore full performance increases
Solution Approach 1:
The patent implements parameter changes by dynamically adjusting multiple parameters including clock frequency, stage duration, and transition timing. The system monitors voltage stability and processor state to optimize the frequency ramp parameters, changing them adaptively to minimize both voltage droop and restoration time based on actual system conditions rather than using fixed predetermined values.
Data Source
AI summary
Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.