Clock Ungating Frequency Ramping to Reduce Voltage Droop
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Solution Overview
Problem
High-speed digital electronics experience voltage droop due to fast clock signal frequency changes, leading to increased power consumption and degraded circuit performance, particularly when clock signals are quickly re-enabled after being gated.
Innovation Solution
A voltage droop mitigation circuit that modulates the clock frequency over a time period using programmable mask patterns or Boolean functions, reducing the impact of clock ungating by ramping the frequency from zero to nominal levels, thereby minimizing voltage transients and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock signals are quickly re-enabled after being gated to restore high-speed operation, then circuit performance is improved, but voltage droop occurs due to sudden current transients
Solution Approach 1:
The patent applies preliminary action by gradually ramping up the clock frequency from zero to the target frequency over a predetermined time period before full operation begins. This gradual frequency increase prevents sudden current transients that would otherwise cause voltage droop, while still achieving the desired high-speed performance in a controlled manner.
2Productivity
If clock frequency is rapidly increased to maximum speed, then productivity is improved, but power consumption increases due to voltage droop and current transients
Solution Approach 1:
The patent implements periodic action by using a predetermined time-based ramp-up schedule that controls the clock frequency increase in stages. The frequency transitions from zero to maximum over a controlled time period, creating a periodic pattern of acceleration that reduces peak current demands and associated power consumption while maintaining overall processing productivity.
Data Source
AI summary
Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.