Clock Unit Jitter Injection for Unauthorized Use Protection
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Solution Overview
Problem
Electronic devices, such as engine control modules, are vulnerable to unauthorized use and illegal modification, which can lead to safety issues and warranty claims due to failed modules being reused or repaired with pirate software, compromising emissions standards and equipment reliability.
Innovation Solution
An electronic device with a clock unit that transitions into a failure analysis mode by introducing high jitter or reducing the clock rate, making it difficult for unauthorized users to reactivate the normal mode, and a disable unit that permanently deactivates the normal mode upon user intervention, ensuring the device cannot be easily reused or reactivated.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the device allows normal operation and reuse, then productivity and ease of operation are improved, but security and reliability deteriorate due to unauthorized use and illegal modification
Solution Approach 1:
The patent applies preliminary action by implementing a security mechanism that is activated in advance when a failure is detected. The disable unit is pre-configured to transition the device from normal operating mode to failure analysis mode upon detecting a failure condition, preventing unauthorized reuse before it can occur. This proactive approach ensures security measures are in place before potential misuse can happen.
Solution Approach 2:
The patent utilizes parameter changes by transitioning the device between different operational states through modifying clock signal parameters. When a failure is detected, the system changes the clock rate or introduces high jitter to the clock signal, effectively changing the operational parameters to render the device unusable in its normal function while allowing analysis. This parameter transformation resolves the contradiction by making the device secure against unauthorized use while maintaining controllability.
2Reliability
If the device transitions to failure analysis mode with high jitter or reduced clock rate, then security against unauthorized use is improved, but ease of operation and productivity deteriorate
Solution Approach 1:
The patent applies segmentation by dividing the device operation into distinct modes: normal operating mode and failure analysis mode. The disable unit acts as a segmentation mechanism that separates these two functional states. When a failure occurs, the system segments the operational flow by transitioning to failure analysis mode, where the device can be analyzed but not used for its intended purpose. This segmentation resolves the contradiction by ensuring security measures don't impact normal productivity while enabling secure analysis when needed.
Solution Approach 2:
The patent implements dynamics by making the device operational state changeable based on detected conditions. The system dynamically transitions between normal mode (high productivity) and failure analysis mode (security-focused) depending on whether a failure is detected. The clock unit dynamically adjusts its output based on the operational mode, providing normal clock signals during normal operation and high-jitter or reduced-rate clocks during failure analysis. This dynamic adaptation resolves the contradiction between security and productivity.
3Reliability
If the disable unit permanently deactivates normal mode, then security against reuse is improved, but the ability to perform failure analysis deteriorates
Solution Approach 1:
The patent applies preliminary action by enabling the disable unit to permanently deactivate normal mode only after failure analysis has been completed. The system is designed so that the transition to permanent deactivation occurs as a preliminary protective measure after the device has been analyzed and determined to be unsuitable for continued use. This timing resolves the contradiction by ensuring failure analysis can be performed before permanent deactivation takes effect.
Solution Approach 2:
The patent implements periodic action through a multi-stage process: first transitioning to failure analysis mode (temporary state), performing analysis, and then optionally transitioning to permanent deactivation (second stage). This periodic or sequential action pattern allows the system to provide both failure analysis capability and security protection at different time periods, resolving the contradiction between these two requirements.
Data Source
AI summary
An electronic device comprising a clock unit and a processing unit connected to the clock unit is described. The clock unit may deliver an output clock signal for operating the processing unit in accordance with the output clock signal. The clock unit may have: a normal mode in which the output clock signal has a low amount of jitter and a normal clock rate to enable normal use of the electronic device, and a failure analysis mode in which the output clock signal has a high amount of jitter or a reduced clock rate, or a high amount of jitter combined with a reduced clock rate, to impede the normal use. The clock unit may be protected against unauthorized re-activation of the normal mode. A method of protecting an electronic device against unauthorized use is also described.