Clock Management Unit No-Code Design for Unified Test Clock Paths
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Solution Overview
Problem
Conventional clock management units in system-on-chip (SoC) designs do not allow for testing of clock components in a test mode, leading to separate functional and test clock paths with different frequencies, resulting in voltage margin discrepancies and increased defect rates during mass production.
Innovation Solution
A no-code approach is used to design a clock management unit where a test clock is generated through the same path as the functional clock, enabling testing of clock components and reducing the need for a separate DFT controller insertion stage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If separate functional and test clock paths are designed with different frequencies, then testing of clock components is simplified, but voltage margin discrepancies occur and defect rates increase during mass production
Solution Approach 1:
The patent merges the functional clock path and test clock path into a single unified clock path. The same clock management unit generates both functional clocks during normal operation and test clocks during testing, ensuring both paths share identical frequency and voltage margin characteristics, thereby eliminating voltage margin discrepancies while maintaining testing capability
Solution Approach 2:
The patent implements dynamic switching capability within the clock management unit that allows the same clock path to serve dual purposes: generating functional clocks at operational frequencies during normal mode, and generating test clocks at test frequencies during test mode. This dynamic reconfiguration enables the system to adapt its function without requiring separate static paths
2Reliability
If a separate DFT controller insertion stage is implemented for testing, then clock component testing is enabled, but device complexity and design time increase
Solution Approach 1:
The clock management unit is designed with multi-functionality, serving both as the functional clock generator during normal operation and as the test clock generator during testing. The same hardware blocks (PLL, clock dividers, multiplexers) perform both functional and test functions, eliminating the need for separate DFT controller insertion and reducing overall device complexity
Solution Approach 2:
The clock management unit performs self-testing by generating test clocks through its own internal paths without requiring external DFT controllers. The unit uses its existing resources (clock sources, dividers, multiplexers) to generate test signals, enabling the system to test itself without additional dedicated testing hardware
Data Source
AI summary
A system and method for designing a clock management unit using a no-code approach capable of testing a clock component that configures a clock management unit and generating a test clock along a functional clock generation path. The at least one instruction includes instructions for: generating a clock instance including a clock source block, a clock control signal block, and a test multiplexer block based on clock component information; generating a test mode controller instance including a test mode TDR block and a test control TDR block corresponding to the test multiplexer block; setting a connection between the test multiplexer block and the test mode controller instance; and generating hardware code based on connection information and the hardware code logic of the clock instance and the test mode controller instance.