Programmable Clock Validation With Glitch Filtering and Duty Check
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Solution Overview
Problem
Existing clock checking methods in communication apparatuses occupy significant resources and fail to effectively filter high-frequent glitches, limiting their reliability and accuracy.
Innovation Solution
A programmable device performs frequency division on a source clock signal to generate a reference clock, determining the validity of a clock signal by comparing counting values of rising edges and high levels against expected values, and calculates the duty ratio, thereby reducing resource usage and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separated apparatuses are used for clock checking on periphery, then clock checking function is achieved, but PCB space and wiring space are significantly occupied
Solution Approach 1:
The patent merges the clock checking function with the existing programmable device (such as an FPGA or CPLD) by utilizing its internal resources like logic elements, counters, and timing resources. This integration eliminates the need for separate peripheral checking circuits, thereby significantly reducing PCB space occupation while maintaining the clock checking capability.
Solution Approach 2:
The programmable device is designed to perform multiple functions: it serves as both the core processing unit for the communication apparatus and the clock checking device. By programming the same device to perform clock validation, frequency measurement, and duty cycle analysis, the system achieves multi-functionality without adding separate dedicated hardware for each function.
2Reliability
If traditional clock checking methods are used, then basic clock validity is checked, but high-frequent glitches cannot be filtered and measurement precision is limited
Solution Approach 1:
The patent implements preliminary filtering of clock signals by using the programmable device to pre-process and validate clock signals before they are used by other system components. The device performs initial validity checks, frequency verification, and duty cycle validation in advance, preventing glitch propagation to downstream circuits and improving overall system reliability.
Solution Approach 2:
The programmable device acts as an intermediary between the clock source and the rest of the system. It mediates clock signal distribution by performing validation, filtering, and conditioning operations, ensuring that only clean, validated clock signals are distributed to other components. This intermediary function enhances measurement precision by isolating the system from high-frequent glitches.
Data Source
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AI summary
The present invention provides a method and apparatus for clock checking, in order to solve the problem of high resource occupation in existing clock checking methods. The method includes: a programmable device for performing frequency division on the source clock signal to obtain a reference clock signal (S101); the programmable device treating the source clock signal as a counting work clock to determine the counting value of rising edges and counting value of high levels of a clock signal being checked during each high level period out of N continuous high levels of the reference clock signal (S102), wherein N is a positive integer; and the programmable device determining whether the clock signal being checked is valid according to the magnitude relationship between the counting value of the high levels of the clock signal being checked during each high level period and a first expected value, as well as the magnitude relationship between the counting value of the rising edges and a second expected value (S103). The technical solution of the present invention occupies fewer resources and improves the reliability of clock checking; the frequency range of the clock signal being checked is relatively wide; and some influence of high frequency spikes of the clock signal being checked can be filtered.