Semiconductor Clock-Voltage Feedback Control for DVFS Stability
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Solution Overview
Problem
Semiconductor devices face challenges in maintaining stable operation speed and minimizing power consumption, as they are influenced by changes in operation circumstances such as PVT conditions, which affects performance and battery life in portable devices.
Innovation Solution
A semiconductor device and system that includes a code generation block, voltage generation block, clock generation block, and feedback delay block, which generate and control internal clock and voltage levels based on external control codes to optimize operation speed and power consumption, using a feedback structure to stabilize operation factors like voltage and frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock signal frequency and voltage power supply are increased to improve operation speed, then the operation speed of the semiconductor circuit increases, but power consumption increases as well
Solution Approach 1:
The patent implements dynamic voltage and frequency scaling (DVFS) by making the voltage supply and clock frequency adjustable rather than fixed. The voltage generation block dynamically changes voltage levels based on control codes, and the clock generation block adjusts clock frequency accordingly, allowing the system to adapt operation parameters to workload requirements and achieve optimal balance between speed and power consumption
Solution Approach 2:
The patent changes the operational parameters (voltage level and clock frequency) of the semiconductor circuit based on control codes that reflect workload conditions. By varying these parameters dynamically - increasing voltage and frequency when high performance is needed, and decreasing them when lower performance suffices - the system optimizes the trade-off between operation speed and power consumption
2Use of energy by moving object
If DVFS technology is used to minimize power consumption, then power consumption decreases, but operation speed may decrease as well
Solution Approach 1:
The patent employs feedback mechanisms where control codes representing workload conditions are used to adjust voltage and frequency settings. The system continuously monitors operational requirements and adjusts parameters accordingly, ensuring that the lowest possible power consumption is achieved while maintaining the operation speed necessary for the current workload
Data Source
AI summary
A semiconductor device includes a code generation block configured to generate an output clock by delaying a reference clock which is inputted from an exterior, control a delay value of the output clock based on a result of comparing phases of the reference clock and a feedback clock, and generate a first control code corresponding to the delay value of the output clock, a voltage generation block configured to generate an internal voltage with a voltage level corresponding to the first control code, a clock generation block configured to generate an internal clock with a frequency corresponding to the first control code, and a feedback delay block configured to generate the feedback clock by delaying the output clock by a delay value corresponding to a second control code.