Clock and Voltage Monitoring Circuit for Autonomous FUSA Security

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Solution Overview

Problem

Computing devices lack effective protection against sophisticated hackers who can manipulate processor signals to perform unauthorized functions, with hardware security remaining largely unprotected.

Innovation Solution

An apparatus that continuously monitors external and internal clock frequencies and voltages, providing functional safety and security by autonomously flagging unexpected changes, using a combination of voltage and clock monitors, narrow range oscillators, voltage reference generators, and power-on detectors to maintain secure operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If hardware security protection mechanisms are implemented, then security against signal manipulation is improved, but device complexity increases

Engineering Contradiction:
Improvehardware securityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The security monitoring function is segmented into separate dedicated circuits: voltage monitor circuitry, clock frequency monitor circuitry, and phase lock monitor circuitry. Each monitor independently checks specific parameters and can trigger security responses without requiring complex integrated processing, thus improving security while managing complexity through functional decomposition.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary security checks by continuously monitoring voltage levels, clock frequencies, and phase lock status before unauthorized manipulation can occur. The monitors detect anomalies in real-time and can preemptively trigger security responses such as resetting the processor or alerting security systems, preventing rather than just responding to attacks.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If continuous monitoring of clock and voltage parameters is implemented, then functional safety is improved, but power consumption increases

Engineering Contradiction:
Improvefunctional safetyVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The monitoring system uses feedback mechanisms where the voltage monitor, clock frequency monitor, and phase lock monitor continuously compare actual parameters against expected ranges. When parameters deviate from normal operation, the feedback loop triggers appropriate security or safety responses. This feedback-based approach enables continuous monitoring with lower power consumption compared to systems that require constant high-level processing of all monitoring data.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If autonomous security monitoring is implemented, then detection accuracy of unauthorized functions is improved, but device complexity increases

Engineering Contradiction:
Improvedetection accuracyVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The monitoring system is designed to autonomously detect and respond to security threats without requiring external intervention or complex centralized processing. Each monitor (voltage, clock frequency, phase lock) independently performs its detection function and can trigger security responses on its own. This self-service capability improves detection accuracy while minimizing the need for complex coordinating logic that would increase overall device complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11461504B2Apparatus for autonomous security and functional safety of clock and voltages including adjustment of a divider ratio
Publication Date: 2022.10.04 INTEL CORP
  • US11461504B2 patent drawing
  • US11461504B2 patent drawing
  • US11461504B2 patent drawing

AI summary

An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.