Clock Wiring Width Tapering for Lower Capacitance and EMI
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Solution Overview
Problem
Conventional semiconductor integrated circuits face performance deterioration due to variations in current density within wirings of the same net, leading to issues such as increased power consumption and reduced speed, which existing optimization methods fail to address.
Innovation Solution
The semiconductor integrated circuit employs a wiring shape that adjusts its width based on distance from the driver or signal frequency, optimizing the wiring shape to reduce current density variations and unnecessary capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the wiring width is designed to be large to ensure sufficient current capacity, then the current density variation is reduced, but the power consumption increases and the speed deteriorates due to unnecessary wiring capacity
Solution Approach 1:
The wiring width is varied locally along the transmission path according to the signal frequency and distance from the driver. High-frequency signal regions have narrower wirings to reduce capacity and power consumption, while low-frequency regions maintain sufficient width for current capacity. This local optimization resolves the contradiction by matching wiring dimensions to actual signal requirements at each position.
Solution Approach 2:
The wiring width parameter is dynamically adjusted based on the signal frequency and position relative to the driver. By changing the wiring width parameter according to frequency bands (e.g., narrower for high-frequency clock signals, wider for low-frequency data signals), the design achieves optimal balance between current density uniformity and power consumption reduction.
2Reliability
If the wiring width is designed to be large to ensure sufficient current capacity, then the current density variation is reduced, but the speed deteriorates due to unnecessary wiring capacity
Solution Approach 1:
The wiring width is optimized locally for different signal types: narrow wirings for high-frequency clock signals to minimize capacity and maximize speed, and wider wirings for low-frequency data signals to maintain current density uniformity. This position-dependent width variation resolves the speed-reliability contradiction.
Solution Approach 2:
The wiring width parameter is changed according to signal frequency and position, creating frequency-specific transmission paths. High-frequency signals traverse narrower wirings for faster transmission, while low-frequency signals use wider wirings for stable current density, thereby achieving both speed and reliability.
3Reliability
If conventional wiring optimization methods are used, then general wiring performance is improved, but the specific problem of current density variation within the same net cannot be solved
Solution Approach 1:
The wiring network is segmented into frequency-based transmission paths with different width characteristics. Clock signal wirings are separated from data signal wirings, and each segment is optimized independently according to its signal type. This segmentation enables specific optimization for current density variation within the same net while maintaining overall wiring performance.
Solution Approach 2:
Different wiring width profiles are applied to different segments of the wiring network based on signal frequency and position. This local quality differentiation allows the design to address current density variation in specific nets while maintaining general wiring optimization, achieving both specialized and general performance improvement.
Data Source
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AI summary
The present disclosure relates to a semiconductor integrated circuit and an electronic apparatus capable of further improving performance. A wiring that forms a transmission network through which the same signal is transmitted has a wiring shape set according to a distance from a driver, and has a wiring width formed to become smaller as the distance from the driver increases. Furthermore, the transmission network is formed by a trunk line to which the driver is connected and which has a large wiring width and branch lines which are branched from the trunk line and has a small wiring width, and the trunk line have a wiring shape set so that a wiring width becomes smaller for every branch portion of the second wirings as a distance from a connection portion of the driver increases. The present technology can be applied to, for example, a clock wiring of a semiconductor integrated circuit.