Clock Wrapper for Dual-Clock Domain Co-Simulation

The patent divides the single clock domain into multiple independent clock domains by introducing separate clock inputs (clk0 and clk1) for different system components. The processor system receives clock clk0 while custom logic receives clock clk1, allowing each component to operate at its required frequency independently. This segmentation resolves the contradiction by maintaining structural simplicity through modular clock distribution while enabling versatile frequency provision for different components.

By segmenting the clock distribution into separate independent clock inputs (clk0 for processor, clk1 for custom logic), the patent eliminates clock jitter propagation that would occur in a single shared clock domain. Each component receives a dedicated clock signal that can be independently stabilized and tuned, ensuring timing requirements are met while keeping the overall structure relatively simple through modular clock management.

The patent implements segmentation of the clocking system by providing separate clock inputs (clk0 and clk1) that can be independently configured. This allows the processor system and custom logic to operate at different frequencies as required by their respective specifications, while the implementation remains straightforward through the use of standard clock distribution techniques and existing hardware co-simulation infrastructure.

By segmenting the clock distribution into separate independent paths (clk0 to processor, clk1 to custom logic), the patent eliminates the need for cascaded Digital Clock Manager (DCM) components that would be required in a single-clock architecture to handle different frequency requirements. Each independent clock path can be directly connected to its target component without intermediate conversion stages, thereby eliminating the clock jitter that would be introduced by cascaded DCM components while maintaining relatively simple clock distribution.