Clocked Analog Switch Circuit for High-Voltage Signal Transfer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional analog switches designed to handle high signal voltages require large circuit scales and high power consumption due to the need for MOS transistors with high withstand voltages, which increases complexity and energy usage.
Innovation Solution
The proposed analog switch employs a clock generation circuit to produce multiple clocks, including opposite polarity clocks, and utilizes N-type and P-type field effect transistors with connected sources and back gates, along with control signal generation circuits to manage the on/off states of these transistors, allowing for efficient switching of high signal voltages without increasing circuit scale or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MOS transistors with high withstand voltage are used to handle high signal voltages, then the analog switch can switch high voltage signals, but the circuit scale and power consumption increase
Solution Approach 1:
The analog switch is divided into multiple switching units, each handling a portion of the voltage range. Multiple NMOS and PMOS transistors are arranged in series/parallel combinations, with each transistor experiencing only a fraction of the total voltage stress, allowing the use of lower-voltage-rated devices while achieving high-voltage switching capability
Solution Approach 2:
The invention changes the voltage distribution parameters across transistors by introducing intermediate voltage nodes and using voltage division techniques. Control voltages are adjusted to ensure each transistor operates within its safe voltage range while collectively handling the full high voltage signal range
2Reliability
If MOS transistors with high withstand voltage are used to handle high signal voltages, then the analog switch can switch high voltage signals, but the power consumption increases
Solution Approach 1:
By segmenting the voltage handling across multiple transistors, each device operates at lower voltage stress levels, reducing the power consumption associated with high-voltage transistor operation while maintaining the overall high-voltage switching capability of the analog switch
3Reliability
If the circuit scale is increased to handle high signal voltages, then the analog switch can switch high voltage signals, but the manufacturing complexity increases
Solution Approach 1:
The segmented transistor arrangement allows each device to be designed and manufactured with standard low-voltage specifications, simplifying the manufacturing process compared to producing fewer high-voltage-rated transistors. The modular structure also facilitates standardized fabrication techniques
Data Source
AI summary
The analog switch includes: a clock generation circuit configured to generate a first clock and a second clock; a transfer circuit including an NMOS transistor having a source and a back gate connected to each other, and a PMOS transistor having a source and a back gate connected to each other, one of which has a drain connected to the source of the other, and a source connected to a signal input terminal, and the other of which has a drain connected to a signal output terminal; a first control signal generation circuit configured to generate a control signal for switching the PMOS transistor based on a voltage at the signal input terminal and the first clock; and a second control signal generation circuit configured to generate a control signal for switching the NMOS transistor based on the voltage at the signal input terminal and the second clock.