Clocked CML Latch Circuit for Lower Power Operation
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Solution Overview
Problem
Current-mode logic (CML) latch circuits consume higher power due to direct current (DC) power paths, which is a disadvantage compared to complementary metal oxide semiconductor (CMOS) counterparts, especially in high-speed applications like communication and computing.
Innovation Solution
Incorporating a switching device between the non-inverting and inverting output nodes of the latch circuit, which is turned on during the pre-evaluate phase to reduce voltage difference and turned off during the regenerate phase, allowing for power consumption comparable to CMOS while maintaining operational speed similar to CML.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If current-mode logic (CML) latch circuits are used for high-speed applications, then operational speed is improved, but power consumption increases due to direct current (DC) power paths
Solution Approach 1:
The patent applies dynamics by transitioning from a static DC power path architecture to a dynamic switched-power architecture. Power delivery to the latch circuit is dynamically controlled through switch elements that selectively connect power supply nodes to different circuit portions based on operational phase, enabling the circuit to adapt its power consumption profile to operational requirements while maintaining high-speed performance
Solution Approach 2:
The patent implements periodic action through clocked power delivery where power supply switches are activated in periodic synchronization with the clock signal. During active phases, power is delivered to support high-speed operation; during inactive or evaluation phases, power delivery is reduced or eliminated. This periodic power gating maintains operational speed when needed while significantly reducing average power consumption
Data Source
AI summary
A latch circuit includes a power supply node, first and second input nodes, and first and second output nodes. A first switching device is coupled between the first and second output nodes and is turned on and off in response to respective first and second states of a clock signal. A first transistor has a source coupled with a common node, a drain coupled with the second output node, and a gate directly coupled with the first input node, and a second transistor has a source coupled with the common node, a drain coupled with the first output node, and a gate directly coupled with the second input node. A second switching device is coupled between the common node and the power supply node and is turned on and off in response to the respective second and first states of the clock signal.