Clocked Comparator Feedback for Faster Low-Power ADCs
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Solution Overview
Problem
High-speed and wide input bandwidth analog-to-digital converters (ADCs) require reduced power consumption and area, but increasing transistor size to enhance drive capability and operating current leads to increased self-capacitance, limiting operational speed and increasing occupied area.
Innovation Solution
Incorporating a fast inverter that provides additional positive feedback to the output node pair, allowing rapid variation of output potentials and reducing power consumption while improving operational speed, by operating in synchronism with a secondary clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If transistor size is increased to enhance drive capability and operating current, then power consumption is reduced, but self-capacitance increases which limits operational speed
Solution Approach 1:
The invention divides the comparator circuit into two independent sections: a first comparator section and a second comparator section. Each section has its own transistors and operates independently with different clock signals. This segmentation allows each section to use optimally sized transistors for its specific function, avoiding the need for large transistors in the entire circuit, thus reducing overall self-capacitance while maintaining adequate drive capability in each section.
Solution Approach 2:
The invention uses dynamic clocking where the first comparator section operates with a first clock signal and the second comparator section operates with a second clock signal. This dynamic operation allows the circuit to achieve high speed operation during the active phase while consuming minimal power during the inactive phase, effectively resolving the trade-off between power consumption and operational speed.
2Speed
If transistor size is increased to enhance drive capability and operating current, then operational speed is improved, but occupied area increases
Solution Approach 1:
By dividing the comparator into two separate sections, each section can use smaller transistors optimized for its specific function rather than requiring large transistors throughout the entire circuit. This segmentation reduces the total occupied area while maintaining high operational speed in each section through optimized transistor sizing and dynamic clocking.
3Speed
If drive capability is enhanced to improve operational speed, then comparison accuracy is improved, but power consumption increases
Solution Approach 1:
The invention employs dynamic clocking where the first comparator section operates with a first clock signal and the second comparator section operates with a second clock signal. During the active phase, drive capability is enhanced for high-speed comparison, while during the inactive phase, power consumption is minimized. This dynamic operation resolves the contradiction between achieving high operational speed through enhanced drive capability and reducing power consumption.
Solution Approach 2:
The comparator sections operate in periodic cycles controlled by their respective clock signals, alternating between active comparison phases and inactive reset phases. This periodic action allows the circuit to achieve high drive capability and operational speed during the active phase while consuming minimal power during the inactive phase, effectively resolving the trade-off between speed and power consumption.
Data Source
AI summary
Increase of power consumption is reduced, and the operational speed is improved. A comparator includes a comparing section which outputs a result of comparison between a first voltage and a second voltage which constitute an input differential signal, a first positive feedback section which operates in synchronism with a first clock signal, amplifies the result from the comparing section, and outputs the amplified result to an output node pair, and a second positive feedback section which operates in synchronism with a second clock signal, and provides positive feedback to the output node pair.