Clocked Comparator Latch Arbitration for Metastability-Free Decisions
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Solution Overview
Problem
Conventional clocked comparators face metastability issues, particularly at high clock frequencies, where small voltage signals take a long time to resolve, leading to errors in high-speed serial link receivers.
Innovation Solution
A clocked comparator circuit comprising an upper-side sampling latch, a lower-side sampling latch, and a decision-arbitrating latch, where the latter receives decisions from both latches and outputs the one resolved earlier, effectively eliminating metastability by using offset voltages to shift decision thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional clocked comparator is used to detect the sign of a voltage signal at high clock frequencies, then the decision-making speed is improved, but metastability errors increase when the voltage signal magnitude is small
Solution Approach 1:
The comparator is divided into two parallel paths: an upper-side sampling latch that compares VX against +VM and a lower-side sampling latch that compares VX against -VM. Each path operates independently to detect different sign conditions, allowing the system to segment the decision-making process and avoid metastability in high-speed operation
Solution Approach 2:
Offset voltages are introduced as intermediary elements to shift the decision thresholds. The upper-side latch uses an offset of +VM and the lower-side latch uses an offset of -VM, creating intermediate comparison levels that prevent direct metastability conflicts when VX is near zero
2Use of energy by moving object
If the voltage signal magnitude is small, then the power consumption is reduced, but the decision resolution time increases significantly
Solution Approach 1:
The offset voltages are applied in advance to the comparison operation, pre-positioning the decision thresholds at ±VM. This preliminary action ensures that even small voltage signals have a sufficient effective magnitude relative to the offset thresholds, enabling faster resolution without increasing signal power
Solution Approach 2:
The decision thresholds are changed from zero-centered to offset-centered at ±VM. By transforming the comparison parameters, small voltage signals that would normally take long to resolve are now compared against offset thresholds that create sufficient voltage differential, reducing resolution time without changing the actual signal power
3Productivity
If the clock frequency is increased to improve data throughput, then the productivity is improved, but the metastability problem becomes more serious
Solution Approach 1:
The decision process is segmented into two parallel comparison paths that operate simultaneously at the high clock frequency. Each path handles a specific sign condition with its own offset threshold, allowing the system to maintain high throughput while distributing the metastability risk across independent paths rather than a single sequential comparator
Solution Approach 2:
The dual-latch structure enables periodic sampling at the clock edge with each latch capturing the voltage signal state relative to its offset threshold. This periodic action synchronized to the clock allows high-frequency operation while the offset thresholds ensure that decisions are made at well-defined voltage levels, reducing metastability
Data Source
AI summary
A clocked comparator includes an upper-side sampling latch configured to output a first decision in accordance with a detection of a sign of an input voltage signal plus an offset voltage at an edge of a clock signal; a lower-side sampling latch configured to output a second decision in accordance with a detection of a sign of the input voltage signal minus the offset voltage at the edge of the clock signal; and a decision-arbitrating latch configured to receive the first decision and the second decision and output a final decision in accordance with whichever one of the first decision and the second decision that is resolved earlier.