Clocked Voltage Comparator Offset Correction With Duty-Cycle Calibration
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Solution Overview
Problem
The miniaturization of integrated circuits has introduced stricter design and manufacturing specifications, leading to challenges with input offset variations in voltage comparator circuits, which affect performance and reliability.
Innovation Solution
A voltage comparator circuit design that alternates clocked comparators between comparison and calibration modes, using multiplexers and an offset control circuit to trim input offsets, ensuring a 100% duty cycle and reducing variations in threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If voltage comparator circuits are miniaturized to reduce device size and power consumption, then integration density and power efficiency are improved, but input offset variations increase due to stricter manufacturing specifications
Solution Approach 1:
The patent applies preliminary action by performing offset calibration during a dedicated calibration phase before the comparator enters its operational comparison phase. The offset control circuit pre-adjusts the threshold voltage to compensate for manufacturing variations, ensuring accurate comparisons during subsequent operations without being affected by the miniaturization-induced variations
2Productivity
If miniaturization is pursued to increase functionality and speed, then device integration is improved, but input offset variations worsen due to manufacturing constraints
Solution Approach 1:
The patent implements feedback through an offset control circuit that receives feedback signals indicating the magnitude of input offset variations. Based on this feedback, the circuit automatically adjusts the threshold voltage of the comparator to compensate for the variations, thereby maintaining manufacturing precision despite miniaturization constraints
3Measurement precision
If offset calibration is performed continuously to maintain accuracy, then measurement precision is improved, but device complexity increases due to additional control circuits
Solution Approach 1:
The patent applies periodic action by performing offset calibration only during a dedicated calibration phase rather than continuously. The comparator alternates between calibration mode and comparison mode, with the offset control circuit activating only during calibration. This periodic approach maintains measurement precision while significantly reducing device complexity compared to continuous calibration schemes
Data Source
AI summary
An integrated circuit includes a first multiplexer, a second multiplexing-input, a first clocked comparator, and a second clocked comparator. A first input node is connected to a first multiplexing-input of the first multiplexer, a first multiplexing-input of the second multiplexer, a first comparing-input of the first clocked comparator, and a first comparing-input of the second clocked comparator. A second input node is connected to a second multiplexing-input of the first multiplexer and a second multiplexing-input of the second multiplexer. An output of the first multiplexer is connected to second comparing-input of the first clocked comparator, and an output of the second multiplexer is connected to a second comparing-input of the second clocked comparator. The integrated circuit also includes an offset control circuit connected to a comparator-output of the first clocked comparator and a comparator-output of the second clocked comparator.