Clocked Comparator Offset Compensation for Faster Low-Power Sensing
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Solution Overview
Problem
Analog comparators face challenges in reducing offset voltage without increasing transistor size, which can lead to slower response times and higher power consumption, and are affected by threshold voltage mismatches between transistors.
Innovation Solution
A clocked comparator circuit operates in multiple phases to reduce offset by compensating for threshold voltage mismatches through diode-connected and positive feedback phases, using NMOS and PMOS transistors to quickly drive output voltages to supply and ground, thereby improving speed and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If transistor size is increased to reduce offset voltage, then offset is reduced, but response time increases and power consumption increases
Solution Approach 1:
The patent applies preliminary action by implementing a calibration phase before the comparison operation. During this calibration phase, the offset voltage is measured and stored. In the subsequent comparison phase, this pre-measured offset information is used to compensate for the offset, allowing accurate comparison without requiring larger transistors, thus maintaining fast response time while reducing offset.
Solution Approach 2:
The patent segments the comparator operation into distinct phases: a calibration phase for measuring and storing offset voltage, and a comparison phase for the actual voltage comparison. This segmentation allows the offset compensation function to be separated from the main comparison function, enabling the use of standard-sized transistors while achieving low offset through the calibration data.
2Measurement precision
If transistor size is increased to reduce offset voltage, then offset is reduced, but power consumption increases
Solution Approach 1:
The calibration phase performs the offset measurement once, storing the result for reuse. This preliminary action eliminates the need for continuous offset compensation circuitry that would consume power, allowing standard-sized transistors to be used without increased power consumption while still achieving offset reduction through the stored calibration data.
Solution Approach 2:
The patent creates a copy of the offset voltage information during calibration and stores it for use during comparison operations. This copied offset data allows the comparator to compensate for offset without requiring the main comparison transistors to be larger, thus avoiding the power consumption penalty that would result from increasing transistor size.
3Measurement precision
If offset voltage is reduced through traditional methods, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent reduces device complexity by performing offset calibration once in advance and storing the result, rather than implementing complex continuous offset cancellation circuitry. This preliminary measurement approach simplifies the main comparison circuit while achieving offset reduction, as the stored calibration data is used to compensate for offset without requiring additional complex components during operation.
Data Source
AI summary
A device includes a first transistor (M1) having a control terminal that is a first comparator input, a first terminal that can be coupled to a voltage source, and a second terminal that provides a first comparator output; a second transistor (M2) having a control terminal that is a second comparator input, a first terminal that can be coupled to the voltage source, and a second terminal that provides a second comparator output; a third transistor (M3) having a control terminal coupled to M1, and a first terminal coupled to ground; a fourth transistor (M4) having a control terminal coupled to M2, and a first terminal coupled to ground; first switches that couple M3 second terminal to M3 control terminal, and M4 second terminal to M4 control terminal; and second switches that couple M3 second terminal to the M2 second terminal, and M4 second terminal to the M1 second terminal.