Clocked Data Recovery Circuit for Glitch-Free Signal Output
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Solution Overview
Problem
Conventional data recovery circuits face challenges in accurately controlling switching timing due to unexpected delays caused by process variations, operating voltage, and temperature, leading to glitches in digital data signal output.
Innovation Solution
A data recovery circuit design that uses two comparison circuits operating on positive and negative clock signals to generate a digital data signal, with a data signal generating circuit that adjusts logic values based on the combination of comparison signals to prevent glitches by maintaining the digital data signal unchanged during certain logic value transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multiplexer is used to alternatively output comparison results of different comparators, then the data recovery circuit can switch between different comparison results, but unexpected delay occurs between output signals of different comparators due to process variation, operating voltage, and temperature, making it difficult for the control circuit to accurately control switching timing, thereby resulting in glitches in the output data signal
Solution Approach 1:
The patent applies preliminary action by pre-configuring the comparison circuits to generate four comparison signals (first, second, third, and fourth) that anticipate all possible comparison outcomes before the actual data transition occurs. The data signal generating circuit is pre-designed with logic to evaluate these signals and determine the correct output logic value in advance, eliminating the need for complex real-time switching control that would be vulnerable to timing delays.
Solution Approach 2:
The patent introduces an intermediary mechanism by using four comparison signals as intermediate representations of the comparison results. Instead of directly switching between comparator outputs using a multiplexer, the circuit uses these intermediate comparison signals to drive the data signal generating circuit, which then produces the final output. This intermediary layer isolates the output from timing variations in the comparators, preventing glitches.
2Measurement precision
If complex control circuitry is used to accurately control the switching timing of the multiplexer, then switching precision may be improved, but the device complexity increases significantly
Solution Approach 1:
The patent extracts the timing control function from the data signal generation process. Instead of using a multiplexer with complex control circuitry to select between comparator outputs based on timing, the invention removes the multiplexer entirely and uses the four comparison signals to directly determine the output logic value. The data signal generating circuit simply evaluates the logic values of these comparison signals according to predetermined rules, eliminating complex timing control while maintaining accuracy.
Solution Approach 2:
The patent applies preliminary action by pre-configuring the comparison circuits to generate four comparison signals that cover all possible comparison outcomes. The data signal generating circuit is pre-designed with logic to evaluate these signals and determine the correct output logic value in advance, eliminating the need for complex real-time switching control that would be vulnerable to timing delays.
Data Source
AI summary
A data recovery circuit includes: a first comparison circuit for comparing two analog data signals to output a first and a second comparison signals having opposite logic values when a positive clock signal stays at an active level, and for configuring the first and second comparison signals to have a same logic value when the positive clock signal stays at an inactive level; a second comparison circuit for comparing the two analog data signals to output a third and a fourth comparison signals having opposite logic values when a negative clock signal stays at the active level, and for configuring the third and fourth comparison signals to have the same logic value when the negative clock signal stays at the inactive level; and a data signal generating circuit for generating a digital data signal according to the first through fourth comparison signals.