Clocked DC Voltage Regulation for Low-Power Supply Stability

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Low-power devices require efficient voltage regulation with minimal power consumption, especially in power-save modes, where existing solutions often fail to optimize power usage effectively.

Innovation Solution

A direct current voltage regulator apparatus that includes a comparator circuit and a clock signal generator, allowing the regulator to switch on only when needed, with adaptive frequency adjustment based on operational conditions, and a reference voltage generator that synchronizes with the clock signal to reduce power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the voltage regulator operates continuously to maintain stable power supply voltage, then the reliability of power supply is improved, but the power consumption increases

Engineering Contradiction:
Improvepower supply stabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The voltage regulator operates periodically rather than continuously. A clock signal generator produces periodic clock signals that trigger the regulator to activate at specific intervals. This periodic operation maintains power supply stability over time while significantly reducing average power consumption compared to continuous operation.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The regulator transitions from a static continuous-operation state to a dynamic state where it switches between active and inactive modes based on clock signals. This dynamic operation allows the system to adapt its power consumption levels while maintaining necessary voltage regulation functionality.

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If the comparator is always on to continuously monitor power supply voltage, then the measurement precision of voltage levels is improved, but the power consumption increases

Engineering Contradiction:
Improvevoltage sampling accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The comparator is activated periodically by clock signals rather than operating continuously. At each activation cycle, the comparator samples the power supply voltage and compares it against a reference level. This periodic sampling maintains adequate voltage monitoring precision while dramatically reducing power consumption compared to continuous monitoring.

Inventive Principle:
Principle #19Periodic action

3Speed

If the regulator operates at high frequency to respond quickly to voltage changes, then the responsiveness is improved, but the power consumption increases

Engineering Contradiction:
Improveresponse speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The operating frequency of the regulator is made dynamic rather than fixed. The clock signal generator adjusts the frequency of activation signals based on system conditions, allowing the regulator to operate at higher frequencies when rapid response is needed and at lower frequencies when power conservation is prioritized.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The time interval between regulator activations is varied as a controllable parameter. By changing the clock signal frequency, the system can adapt the regulator's response speed to match actual power supply conditions and power availability, optimizing the trade-off between responsiveness and power consumption.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12189407B2DC voltage regulator for low-power device
Publication Date: 2025.01.07 NORDIC SEMICONDUCTOR
  • US12189407B2 patent drawing
  • US12189407B2 patent drawing
  • US12189407B2 patent drawing

AI summary

This document describes a solution for low-power voltage regulation. According to an aspect, there is provided an apparatus comprising: a supply voltage regulator circuit configured to regulate a power supply voltage of a circuit; a comparator circuit coupled to the power supply voltage and configured to sample the power supply voltage, to compare the sampled power supply voltage with a reference voltage and, if the sampled power supply voltage is below the reference voltage, to enable the supply voltage regulator circuit to charge the power supply voltage, wherein the comparator is switched on and off in response to a clock signal; and a clock signal generator circuit configured to generate the clock signal.