Clocked Flip-Flop Delay Circuit for Stable Signal Timing
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Solution Overview
Problem
Existing semiconductor delay circuits are adversely affected by PVT variations, leading to unstable delay times and limited signal margins, which can impact high-speed operation due to the large area occupied by impedance elements and transistor characteristic changes.
Innovation Solution
A delay circuit that includes a delay unit performing flip-flop operations in synchronization with a clock signal to generate multiple delayed signals, and an option unit that selects one of these signals based on select signals, reducing sensitivity to PVT variations and stabilizing delay times through edge-triggering operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If RC delay mechanism with resistors and capacitors is used, then delay time can be controlled, but area occupied increases and integration degree decreases
Solution Approach 1:
The patent replaces the RC delay mechanism (analog circuit) with a digital delay mechanism using D flip-flops and clock signals. This substitution transforms the delay implementation from continuous analog time constants to discrete digital clock cycles, eliminating the need for large-area resistors and capacitors while maintaining controllable delay functionality through clock frequency and flip-flop staging.
Solution Approach 2:
The patent changes the fundamental parameter for delay control from RC time constants to clock signal frequency and flip-flop configuration. By adjusting the clock frequency and the number of flip-flop stages, the delay time can be precisely controlled without requiring large physical impedance elements, thus resolving the area occupation problem.
2Adaptability or versatility
If delay time is controlled by current flow through transistors, then delay can be adjusted, but delay time becomes unstable under PVT variations
Solution Approach 1:
The patent introduces periodic clock signals to drive the D flip-flops, replacing continuous current flow control with discrete periodic sampling. The delay time is determined by the number of clock cycles and flip-flop stages, which are inherently stable against PVT variations compared to analog current mirrors. This periodic digital action provides both adjustability (through clock frequency and staging) and stability (through digital immunity to analog variations).
Solution Approach 2:
The patent substitutes the analog transistor current flow mechanism with a digital clocked flip-flop system. This replacement eliminates the sensitivity to PVT variations that plagues analog current mirrors, as digital logic levels and clock timing are far more robust against process, voltage, and temperature changes.
3Manufacturing precision
If multiple impedance elements are used for delay, then delay precision can be achieved, but device complexity increases
Solution Approach 1:
The patent changes the approach to delay precision from analog component value precision to digital counting precision. Instead of requiring precise RC time constants, the delay is determined by counting clock cycles through a series of flip-flops, where precision is achieved through the integer number of stages rather than continuous component values. This digital counting approach simplifies the circuit while maintaining or improving precision.
Data Source
AI summary
A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal.